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move from ultisnips format to snipmate format upon request

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This commit is contained in:
Boone Severson 2015-03-20 08:23:01 -07:00
parent e37267bce6
commit f20a1c4c4e
2 changed files with 127 additions and 156 deletions
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156
UltiSnips/systemverilog.snippets
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@ -1,156 +0,0 @@
priority -50
##########################
# SystemVerilog Snippets #
##########################
snippet if "If statement"
if (${1}) begin
$0
end
endsnippet
snippet ife "If/else statements"
if (${1}) begin
$0
end
else begin
end
endsnippet
snippet eif "Else if statement"
else if (${1}) begin
$0
end
endsnippet
snippet el "Else statement"
else begin
$0
end
endsnippet
snippet wh "While statement"
while (${1}) begin
$0
end
endsnippet
snippet rep "Repeat loop"
repeat (${1}) begin
$0
end
endsnippet
snippet fe "Foreach loop"
foreach (${1}) begin
$0
end
endsnippet
snippet dowh "Do-while statement"
do begin
$0
end while (${1});
endsnippet
snippet case "Case statement"
case (${1})
{$2}: begin
$0
end
default: begin
end
endcase
endsnippet
snippet casez "CaseZ statement"
casez (${1})
{$2}: begin
$0
end
default: begin
end
endcase
endsnippet
snippet alc "Combinational always block"
always_comb begin ${1:: statement_label}
$0
end $1
endsnippet
snippet alff "Sequential logic"
always_ff @(posedge ${1:clk}) begin ${2:: statement_label}
$0
end $2
endsnippet
snippet all "Latched logic"
always_latch begin ${1:: statement_label}
$0
end $1
endsnippet
snippet mod "Module block"
module ${1:module_name} ();
$0
endmodule : $1
endsnippet
snippet cl "Class"
class ${1:module_name};
// data or class properties
$0
// initialization
function new();
endfunction : new
endmodule : $1
endsnippet
snippet types "Typedef structure"
typedef struct {
$0
} ${1:name_t};
endsnippet
snippet prog "Program block"
program ${1:program_name} ();
$0
endprogram : $1
endsnippet
snippet intf "Interface block"
interface ${1:program_name} ();
// nets
$0
// clocking
// modports
endinterface : $1
endsnippet
snippet clock "Clocking Block"
clocking ${1:clocking_name} @(${2:posedge} ${3:clk});
$0
endclocking : $1
endsnippet
snippet cg "Covergroup construct"
covergroup ${1:group_name} @(${2:posedge} ${3:clk});
$0
endgroup : $1
endsnippet
snippet pkg "Package declaration"
package ${1:package_name};
$0
endpackage : $1
endsnippet
# vim:ft=snippets:

127
snippets/systemverilog.snippets Normal file
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@ -0,0 +1,127 @@
# if statement
snippet if
if (${1}) begin
${0}
end
# If/else statements
snippet ife
if (${1}) begin
${2}
end
else begin
${1}
end
# Else if statement
snippet eif
else if (${1}) begin
${0}
end
#Else statement
snippet el
else begin
${0}
end
# While statement
snippet wh
while (${1}) begin
${0}
end
# Repeat Loop
snippet rep
repeat (${1}) begin
${0}
end
# Foreach Loopo
snippet fe
foreach (${1}) begin
${0}
end
# Do-while statement
snippet dowh
do begin
${0}
end while (${1});
# Case statement
snippet case
case (${1})
{$2}: begin
${0}
end
default: begin
end
endcase
# CaseZ statement
snippet casez
casez (${1})
{$2}: begin
${0}
end
default: begin
end
endcase
# Combinational always block
snippet alc
always_comb begin ${1:: statement_label}
${0}
end $1
# Sequential logic
snippet alff
always_ff @(posedge ${1:clk}) begin ${2:: statement_label}
${0}
end $2
# Latched logic
snippet all
always_latch begin ${1:: statement_label}
${0}
end $1
# Module block
snippet mod
module ${1:module_name} (${2});
${0}
endmodule : $1
# Class
snippet cl
class ${1:module_name};
// data or class properties
${0}
// initialization
function new();
endfunction : new
endmodule : $1
# Typedef structure
snippet types
typedef struct {
${0}
} ${1:name_t};
# Program block
snippet prog
program ${1:program_name} ();
${0}
endprogram : $1
# Interface block
snippet intf
interface ${1:program_name} ();
// nets
${0}
// clocking
// modports
endinterface : $1
# Clocking Block
snippet clock
clocking ${1:clocking_name} @(${2:posedge} ${3:clk});
${0}
endclocking : $1
# Covergroup construct
snippet cg
covergroup ${1:group_name} @(${2:posedge} ${3:clk});
${0}
endgroup : $1
# Package declaration
snippet pkg
package ${1:package_name};
${0}
endpackage : $1