Add verilog snippets and refactor systemverilog removing duplicates
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@ -1,37 +1,6 @@
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# if statement
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snippet if
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if (${1}) begin
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${0}
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end
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# If/else statements
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snippet ife
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if (${1}) begin
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${2}
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end
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else begin
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${1}
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end
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# Else if statement
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snippet eif
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else if (${1}) begin
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${0}
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end
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#Else statement
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snippet el
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else begin
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${0}
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end
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# While statement
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snippet wh
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while (${1}) begin
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${0}
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end
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# Repeat Loop
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snippet rep
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repeat (${1}) begin
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${0}
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end
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# Foreach Loopo
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extends verilog
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# Foreach Loop
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snippet fe
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foreach (${1}) begin
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${0}
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@ -41,24 +10,6 @@ snippet dowh
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do begin
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${0}
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end while (${1});
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# Case statement
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snippet case
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case (${1})
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{$2}: begin
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${0}
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end
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default: begin
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end
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endcase
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# CaseZ statement
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snippet casez
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casez (${1})
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{$2}: begin
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${0}
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end
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default: begin
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end
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endcase
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# Combinational always block
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snippet alc
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always_comb begin ${1:: statement_label}
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@ -74,11 +25,6 @@ snippet all
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always_latch begin ${1:: statement_label}
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${0}
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end $1
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# Module block
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snippet mod
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module ${1:module_name} (${2});
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${0}
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endmodule : $1
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# Class
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snippet cl
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class ${1:class_name};
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63
snippets/verilog.snippets
Normal file
63
snippets/verilog.snippets
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@ -0,0 +1,63 @@
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# if statement
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snippet if
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if (${1}) begin
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${0}
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end
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# If/else statements
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snippet ife
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if (${1}) begin
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${2}
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end
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else begin
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${1}
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end
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# Else if statement
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snippet eif
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else if (${1}) begin
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${0}
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end
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#Else statement
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snippet el
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else begin
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${0}
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end
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# While statement
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snippet wh
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while (${1}) begin
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${0}
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end
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# Repeat Loop
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snippet rep
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repeat (${1}) begin
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${0}
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end
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# Case statement
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snippet case
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case (${1:/* variable */})
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${2:/* value */}: begin
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${3}
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end
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default: begin
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${4}
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end
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endcase
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# CaseZ statement
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snippet casez
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casez (${1:/* variable */})
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${2:/* value */}: begin
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${3}
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end
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default: begin
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${4}
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end
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endcase
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# Always block
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snippet al
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always @(${1:/* sensitive list */}) begin
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${0}
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end
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# Module block
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snippet mod
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module ${1:module_name} (${2});
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${0}
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endmodule
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