265 lines
9.3 KiB
VimL
265 lines
9.3 KiB
VimL
if !exists('g:polyglot_disabled') || index(g:polyglot_disabled, 'vim') == -1
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" Vim syntax file
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" Language: VHDL [VHSIC (Very High Speed Integrated Circuit) Hardware Description Language]
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" Maintainer: Daniel Kho <daniel.kho@tauhop.com>
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" Previous Maintainer: Czo <Olivier.Sirol@lip6.fr>
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" Credits: Stephan Hegel <stephan.hegel@snc.siemens.com.cn>
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" Last Changed: 2016 Mar 05 by Daniel Kho
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" quit when a syntax file was already loaded
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if exists("b:current_syntax")
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finish
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endif
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let s:cpo_save = &cpo
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set cpo&vim
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" case is not significant
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syn case ignore
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" VHDL keywords
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syn keyword vhdlStatement access after alias all assert
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syn keyword vhdlStatement architecture array attribute
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syn keyword vhdlStatement assume assume_guarantee
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syn keyword vhdlStatement begin block body buffer bus
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syn keyword vhdlStatement case component configuration constant
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syn keyword vhdlStatement context cover
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syn keyword vhdlStatement default disconnect downto
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syn keyword vhdlStatement elsif end entity exit
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syn keyword vhdlStatement file for function
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syn keyword vhdlStatement fairness force
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syn keyword vhdlStatement generate generic group guarded
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syn keyword vhdlStatement impure in inertial inout is
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syn keyword vhdlStatement label library linkage literal loop
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syn keyword vhdlStatement map
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syn keyword vhdlStatement new next null
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syn keyword vhdlStatement of on open others out
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syn keyword vhdlStatement package port postponed procedure process pure
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syn keyword vhdlStatement parameter property protected
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syn keyword vhdlStatement range record register reject report return
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syn keyword vhdlStatement release restrict restrict_guarantee
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syn keyword vhdlStatement select severity signal shared
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syn keyword vhdlStatement subtype
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syn keyword vhdlStatement sequence strong
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syn keyword vhdlStatement then to transport type
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syn keyword vhdlStatement unaffected units until use
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syn keyword vhdlStatement variable
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syn keyword vhdlStatement vmode vprop vunit
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syn keyword vhdlStatement wait when while with
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syn keyword vhdlStatement note warning error failure
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" Linting of conditionals.
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syn match vhdlStatement "\<\(if\|else\)\>"
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syn match vhdlError "\<else\s\+if\>"
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" Types and type qualifiers
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" Predefined standard VHDL types
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syn match vhdlType "\<bit\>\'\="
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syn match vhdlType "\<boolean\>\'\="
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syn match vhdlType "\<natural\>\'\="
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syn match vhdlType "\<positive\>\'\="
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syn match vhdlType "\<integer\>\'\="
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syn match vhdlType "\<real\>\'\="
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syn match vhdlType "\<time\>\'\="
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syn match vhdlType "\<bit_vector\>\'\="
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syn match vhdlType "\<boolean_vector\>\'\="
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syn match vhdlType "\<integer_vector\>\'\="
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syn match vhdlType "\<real_vector\>\'\="
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syn match vhdlType "\<time_vector\>\'\="
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syn match vhdlType "\<character\>\'\="
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syn match vhdlType "\<string\>\'\="
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"syn keyword vhdlType severity_level
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syn keyword vhdlType line
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syn keyword vhdlType text
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" Predefined standard IEEE VHDL types
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syn match vhdlType "\<std_ulogic\>\'\="
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syn match vhdlType "\<std_logic\>\'\="
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syn match vhdlType "\<std_ulogic_vector\>\'\="
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syn match vhdlType "\<std_logic_vector\>\'\="
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syn match vhdlType "\<unresolved_signed\>\'\="
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syn match vhdlType "\<unresolved_unsigned\>\'\="
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syn match vhdlType "\<u_signed\>\'\="
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syn match vhdlType "\<u_unsigned\>\'\="
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syn match vhdlType "\<signed\>\'\="
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syn match vhdlType "\<unsigned\>\'\="
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" array attributes
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syn match vhdlAttribute "\'high"
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syn match vhdlAttribute "\'left"
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syn match vhdlAttribute "\'length"
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syn match vhdlAttribute "\'low"
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syn match vhdlAttribute "\'range"
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syn match vhdlAttribute "\'reverse_range"
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syn match vhdlAttribute "\'right"
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syn match vhdlAttribute "\'ascending"
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" block attributes
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syn match vhdlAttribute "\'simple_name"
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syn match vhdlAttribute "\'instance_name"
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syn match vhdlAttribute "\'path_name"
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syn match vhdlAttribute "\'foreign" " VHPI
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" signal attribute
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syn match vhdlAttribute "\'active"
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syn match vhdlAttribute "\'delayed"
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syn match vhdlAttribute "\'event"
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syn match vhdlAttribute "\'last_active"
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syn match vhdlAttribute "\'last_event"
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syn match vhdlAttribute "\'last_value"
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syn match vhdlAttribute "\'quiet"
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syn match vhdlAttribute "\'stable"
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syn match vhdlAttribute "\'transaction"
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syn match vhdlAttribute "\'driving"
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syn match vhdlAttribute "\'driving_value"
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" type attributes
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syn match vhdlAttribute "\'base"
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syn match vhdlAttribute "\'subtype"
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syn match vhdlAttribute "\'element"
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syn match vhdlAttribute "\'leftof"
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syn match vhdlAttribute "\'pos"
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syn match vhdlAttribute "\'pred"
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syn match vhdlAttribute "\'rightof"
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syn match vhdlAttribute "\'succ"
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syn match vhdlAttribute "\'val"
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syn match vhdlAttribute "\'image"
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syn match vhdlAttribute "\'value"
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syn keyword vhdlBoolean true false
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" for this vector values case is significant
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syn case match
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" Values for standard VHDL types
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syn match vhdlVector "\'[0L1HXWZU\-\?]\'"
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syn case ignore
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syn match vhdlVector "B\"[01_]\+\""
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syn match vhdlVector "O\"[0-7_]\+\""
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syn match vhdlVector "X\"[0-9a-f_]\+\""
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syn match vhdlCharacter "'.'"
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syn region vhdlString start=+"+ end=+"+
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" floating numbers
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syn match vhdlNumber "-\=\<\d\+\.\d\+\(E[+\-]\=\d\+\)\>"
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syn match vhdlNumber "-\=\<\d\+\.\d\+\>"
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syn match vhdlNumber "0*2#[01_]\+\.[01_]\+#\(E[+\-]\=\d\+\)\="
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syn match vhdlNumber "0*16#[0-9a-f_]\+\.[0-9a-f_]\+#\(E[+\-]\=\d\+\)\="
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" integer numbers
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syn match vhdlNumber "-\=\<\d\+\(E[+\-]\=\d\+\)\>"
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syn match vhdlNumber "-\=\<\d\+\>"
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syn match vhdlNumber "0*2#[01_]\+#\(E[+\-]\=\d\+\)\="
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syn match vhdlNumber "0*16#[0-9a-f_]\+#\(E[+\-]\=\d\+\)\="
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" operators
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syn keyword vhdlOperator and nand or nor xor xnor
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syn keyword vhdlOperator rol ror sla sll sra srl
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syn keyword vhdlOperator mod rem abs not
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" Concatenation and math operators
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syn match vhdlOperator "&\|+\|-\|\*\|\/"
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" Equality and comparison operators
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syn match vhdlOperator "=\|\/=\|>\|<\|>="
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" Assignment operators
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syn match vhdlOperator "<=\|:="
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syn match vhdlOperator "=>"
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" VHDL-2008 conversion, matching equality/non-equality operators
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syn match vhdlOperator "??\|?=\|?\/=\|?<\|?<=\|?>\|?>="
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" VHDL-2008 external names
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syn match vhdlOperator "<<\|>>"
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" Linting for illegal operators
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" '='
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syn match vhdlError "\(=\)[<=&+\-\*\/\\]\+"
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syn match vhdlError "[=&+\-\*\\]\+\(=\)"
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" '>', '<'
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" Allow external names: '<< ... >>'
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syn match vhdlError "\(>\)[<&+\-\/\\]\+"
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syn match vhdlError "[&+\-\/\\]\+\(>\)"
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syn match vhdlError "\(<\)[&+\-\/\\]\+"
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syn match vhdlError "[>=&+\-\/\\]\+\(<\)"
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" Covers most operators
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" support negative sign after operators. E.g. q<=-b;
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syn match vhdlError "\(&\|+\|\-\|\*\*\|\/=\|??\|?=\|?\/=\|?<=\|?>=\|>=\|<=\|:=\|=>\)[<>=&+\*\\?:]\+"
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syn match vhdlError "[<>=&+\-\*\\:]\+\(&\|+\|\*\*\|\/=\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|>=\|<=\|:=\|=>\)"
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syn match vhdlError "\(?<\|?>\)[<>&+\*\/\\?:]\+"
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syn match vhdlError "\(<<\|>>\)[<>&+\*\/\\?:]\+"
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"syn match vhdlError "[?]\+\(&\|+\|\-\|\*\*\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|:=\|=>\)"
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" '/'
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syn match vhdlError "\(\/\)[<>&+\-\*\/\\?:]\+"
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syn match vhdlError "[<>=&+\-\*\/\\:]\+\(\/\)"
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syn match vhdlSpecial "<>"
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syn match vhdlSpecial "[().,;]"
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" time
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syn match vhdlTime "\<\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>"
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syn match vhdlTime "\<\d\+\.\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>"
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syn case match
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syn keyword vhdlTodo contained TODO NOTE
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syn keyword vhdlFixme contained FIXME
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syn case ignore
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syn region vhdlComment start="/\*" end="\*/" contains=vhdlTodo,vhdlFixme,@Spell
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syn match vhdlComment "\(^\|\s\)--.*" contains=vhdlTodo,vhdlFixme,@Spell
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" Standard IEEE P1076.6 preprocessor directives (metacomments).
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syn match vhdlPreProc "/\*\s*rtl_synthesis\s\+\(on\|off\)\s*\*/"
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syn match vhdlPreProc "\(^\|\s\)--\s*rtl_synthesis\s\+\(on\|off\)\s*"
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syn match vhdlPreProc "/\*\s*rtl_syn\s\+\(on\|off\)\s*\*/"
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syn match vhdlPreProc "\(^\|\s\)--\s*rtl_syn\s\+\(on\|off\)\s*"
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" Industry-standard directives. These are not standard VHDL, but are commonly
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" used in the industry.
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syn match vhdlPreProc "/\*\s*synthesis\s\+translate_\(on\|off\)\s*\*/"
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"syn match vhdlPreProc "/\*\s*simulation\s\+translate_\(on\|off\)\s*\*/"
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syn match vhdlPreProc "/\*\s*pragma\s\+translate_\(on\|off\)\s*\*/"
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syn match vhdlPreProc "/\*\s*pragma\s\+synthesis_\(on\|off\)\s*\*/"
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syn match vhdlPreProc "/\*\s*synopsys\s\+translate_\(on\|off\)\s*\*/"
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syn match vhdlPreProc "\(^\|\s\)--\s*synthesis\s\+translate_\(on\|off\)\s*"
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"syn match vhdlPreProc "\(^\|\s\)--\s*simulation\s\+translate_\(on\|off\)\s*"
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syn match vhdlPreProc "\(^\|\s\)--\s*pragma\s\+translate_\(on\|off\)\s*"
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syn match vhdlPreProc "\(^\|\s\)--\s*pragma\s\+synthesis_\(on\|off\)\s*"
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syn match vhdlPreProc "\(^\|\s\)--\s*synopsys\s\+translate_\(on\|off\)\s*"
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"Modify the following as needed. The trade-off is performance versus functionality.
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syn sync minlines=600
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" Define the default highlighting.
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" Only when an item doesn't have highlighting yet
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hi def link vhdlSpecial Special
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hi def link vhdlStatement Statement
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hi def link vhdlCharacter Character
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hi def link vhdlString String
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hi def link vhdlVector Number
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hi def link vhdlBoolean Number
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hi def link vhdlTodo Todo
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hi def link vhdlFixme Fixme
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hi def link vhdlComment Comment
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hi def link vhdlNumber Number
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hi def link vhdlTime Number
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hi def link vhdlType Type
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hi def link vhdlOperator Operator
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hi def link vhdlError Error
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hi def link vhdlAttribute Special
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hi def link vhdlPreProc PreProc
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let b:current_syntax = "vhdl"
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let &cpo = s:cpo_save
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unlet s:cpo_save
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" vim: ts=8
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endif
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