124 lines
5.0 KiB
VimL
124 lines
5.0 KiB
VimL
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if !exists('g:polyglot_disabled') || index(g:polyglot_disabled, 'vim') == -1
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" Vim syntax file
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" Language: Verilog
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" Maintainer: Mun Johl <Mun.Johl@emulex.com>
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" Last Update: Wed Jul 20 16:04:19 PDT 2011
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" quit when a syntax file was already loaded
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if exists("b:current_syntax")
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finish
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endif
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" Set the local value of the 'iskeyword' option.
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" NOTE: '?' was added so that verilogNumber would be processed correctly when
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" '?' is the last character of the number.
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setlocal iskeyword=@,48-57,63,_,192-255
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" A bunch of useful Verilog keywords
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syn keyword verilogStatement always and assign automatic buf
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syn keyword verilogStatement bufif0 bufif1 cell cmos
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syn keyword verilogStatement config deassign defparam design
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syn keyword verilogStatement disable edge endconfig
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syn keyword verilogStatement endfunction endgenerate endmodule
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syn keyword verilogStatement endprimitive endspecify endtable endtask
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syn keyword verilogStatement event force function
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syn keyword verilogStatement generate genvar highz0 highz1 ifnone
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syn keyword verilogStatement incdir include initial inout input
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syn keyword verilogStatement instance integer large liblist
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syn keyword verilogStatement library localparam macromodule medium
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syn keyword verilogStatement module nand negedge nmos nor
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syn keyword verilogStatement noshowcancelled not notif0 notif1 or
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syn keyword verilogStatement output parameter pmos posedge primitive
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syn keyword verilogStatement pull0 pull1 pulldown pullup
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syn keyword verilogStatement pulsestyle_onevent pulsestyle_ondetect
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syn keyword verilogStatement rcmos real realtime reg release
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syn keyword verilogStatement rnmos rpmos rtran rtranif0 rtranif1
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syn keyword verilogStatement scalared showcancelled signed small
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syn keyword verilogStatement specify specparam strong0 strong1
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syn keyword verilogStatement supply0 supply1 table task time tran
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syn keyword verilogStatement tranif0 tranif1 tri tri0 tri1 triand
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syn keyword verilogStatement trior trireg unsigned use vectored wait
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syn keyword verilogStatement wand weak0 weak1 wire wor xnor xor
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syn keyword verilogLabel begin end fork join
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syn keyword verilogConditional if else case casex casez default endcase
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syn keyword verilogRepeat forever repeat while for
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syn keyword verilogTodo contained TODO FIXME
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syn match verilogOperator "[&|~><!)(*#%@+/=?:;}{,.\^\-\[\]]"
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syn region verilogComment start="/\*" end="\*/" contains=verilogTodo,@Spell
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syn match verilogComment "//.*" contains=verilogTodo,@Spell
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"syn match verilogGlobal "`[a-zA-Z0-9_]\+\>"
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syn match verilogGlobal "`celldefine"
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syn match verilogGlobal "`default_nettype"
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syn match verilogGlobal "`define"
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syn match verilogGlobal "`else"
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syn match verilogGlobal "`elsif"
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syn match verilogGlobal "`endcelldefine"
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syn match verilogGlobal "`endif"
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syn match verilogGlobal "`ifdef"
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syn match verilogGlobal "`ifndef"
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syn match verilogGlobal "`include"
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syn match verilogGlobal "`line"
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syn match verilogGlobal "`nounconnected_drive"
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syn match verilogGlobal "`resetall"
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syn match verilogGlobal "`timescale"
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syn match verilogGlobal "`unconnected_drive"
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syn match verilogGlobal "`undef"
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syn match verilogGlobal "$[a-zA-Z0-9_]\+\>"
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syn match verilogConstant "\<[A-Z][A-Z0-9_]\+\>"
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syn match verilogNumber "\(\<\d\+\|\)'[sS]\?[bB]\s*[0-1_xXzZ?]\+\>"
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syn match verilogNumber "\(\<\d\+\|\)'[sS]\?[oO]\s*[0-7_xXzZ?]\+\>"
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syn match verilogNumber "\(\<\d\+\|\)'[sS]\?[dD]\s*[0-9_xXzZ?]\+\>"
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syn match verilogNumber "\(\<\d\+\|\)'[sS]\?[hH]\s*[0-9a-fA-F_xXzZ?]\+\>"
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syn match verilogNumber "\<[+-]\=[0-9_]\+\(\.[0-9_]*\|\)\(e[0-9_]*\|\)\>"
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syn region verilogString start=+"+ skip=+\\"+ end=+"+ contains=verilogEscape,@Spell
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syn match verilogEscape +\\[nt"\\]+ contained
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syn match verilogEscape "\\\o\o\=\o\=" contained
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" Directives
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syn match verilogDirective "//\s*synopsys\>.*$"
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syn region verilogDirective start="/\*\s*synopsys\>" end="\*/"
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syn region verilogDirective start="//\s*synopsys dc_script_begin\>" end="//\s*synopsys dc_script_end\>"
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syn match verilogDirective "//\s*\$s\>.*$"
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syn region verilogDirective start="/\*\s*\$s\>" end="\*/"
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syn region verilogDirective start="//\s*\$s dc_script_begin\>" end="//\s*\$s dc_script_end\>"
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"Modify the following as needed. The trade-off is performance versus
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"functionality.
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syn sync minlines=50
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" Define the default highlighting.
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" Only when an item doesn't have highlighting yet
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" The default highlighting.
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hi def link verilogCharacter Character
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hi def link verilogConditional Conditional
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hi def link verilogRepeat Repeat
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hi def link verilogString String
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hi def link verilogTodo Todo
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hi def link verilogComment Comment
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hi def link verilogConstant Constant
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hi def link verilogLabel Label
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hi def link verilogNumber Number
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hi def link verilogOperator Special
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hi def link verilogStatement Statement
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hi def link verilogGlobal Define
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hi def link verilogDirective SpecialComment
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hi def link verilogEscape Special
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let b:current_syntax = "verilog"
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" vim: ts=8
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endif
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