142 lines
5.0 KiB
C++
142 lines
5.0 KiB
C++
//===-- HexagonVarargsCallingConvention.h - Calling Conventions -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the functions that assign locations to outgoing function
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// arguments. Adapted from the target independent version but this handles
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// calls to varargs functions
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//
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//===----------------------------------------------------------------------===//
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//
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static bool RetCC_Hexagon32_VarArgs(unsigned ValNo, EVT ValVT,
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EVT LocVT, CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags,
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Hexagon_CCState &State,
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int NonVarArgsParams,
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int CurrentParam,
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bool ForceMem);
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static bool CC_Hexagon32_VarArgs(unsigned ValNo, EVT ValVT,
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EVT LocVT, CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags,
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Hexagon_CCState &State,
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int NonVarArgsParams,
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int CurrentParam,
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bool ForceMem) {
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unsigned ByValSize = 0;
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if (ArgFlags.isByVal() &&
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((ByValSize = ArgFlags.getByValSize()) >
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(MVT(MVT::i64).getSizeInBits() / 8))) {
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ForceMem = true;
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}
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// Only assign registers for named (non varargs) arguments
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if ( !ForceMem && ((NonVarArgsParams == -1) || (CurrentParam <=
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NonVarArgsParams))) {
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if (LocVT == MVT::i32 ||
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LocVT == MVT::i16 ||
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LocVT == MVT::i8 ||
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LocVT == MVT::f32) {
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static const unsigned RegList1[] = {
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Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
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Hexagon::R5
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};
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if (unsigned Reg = State.AllocateReg(RegList1, 6)) {
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State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg,
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LocVT.getSimpleVT(), LocInfo));
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return false;
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}
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}
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if (LocVT == MVT::i64 ||
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LocVT == MVT::f64) {
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static const unsigned RegList2[] = {
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Hexagon::D0, Hexagon::D1, Hexagon::D2
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};
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if (unsigned Reg = State.AllocateReg(RegList2, 3)) {
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State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg,
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LocVT.getSimpleVT(), LocInfo));
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return false;
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}
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}
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}
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const Type* ArgTy = LocVT.getTypeForEVT(State.getContext());
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unsigned Alignment =
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State.getTarget().getTargetData()->getABITypeAlignment(ArgTy);
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unsigned Size =
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State.getTarget().getTargetData()->getTypeSizeInBits(ArgTy) / 8;
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// If it's passed by value, then we need the size of the aggregate not of
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// the pointer.
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if (ArgFlags.isByVal()) {
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Size = ByValSize;
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// Hexagon_TODO: Get the alignment of the contained type here.
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Alignment = 8;
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}
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unsigned Offset3 = State.AllocateStack(Size, Alignment);
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State.addLoc(CCValAssign::getMem(ValNo, ValVT.getSimpleVT(), Offset3,
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LocVT.getSimpleVT(), LocInfo));
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return false;
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}
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static bool RetCC_Hexagon32_VarArgs(unsigned ValNo, EVT ValVT,
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EVT LocVT, CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags,
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Hexagon_CCState &State,
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int NonVarArgsParams,
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int CurrentParam,
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bool ForceMem) {
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if (LocVT == MVT::i32 ||
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LocVT == MVT::f32) {
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static const unsigned RegList1[] = {
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Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
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Hexagon::R5
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};
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if (unsigned Reg = State.AllocateReg(RegList1, 6)) {
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State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg,
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LocVT.getSimpleVT(), LocInfo));
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return false;
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}
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}
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if (LocVT == MVT::i64 ||
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LocVT == MVT::f64) {
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static const unsigned RegList2[] = {
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Hexagon::D0, Hexagon::D1, Hexagon::D2
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};
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if (unsigned Reg = State.AllocateReg(RegList2, 3)) {
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State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg,
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LocVT.getSimpleVT(), LocInfo));
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return false;
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}
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}
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const Type* ArgTy = LocVT.getTypeForEVT(State.getContext());
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unsigned Alignment =
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State.getTarget().getTargetData()->getABITypeAlignment(ArgTy);
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unsigned Size =
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State.getTarget().getTargetData()->getTypeSizeInBits(ArgTy) / 8;
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unsigned Offset3 = State.AllocateStack(Size, Alignment);
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State.addLoc(CCValAssign::getMem(ValNo, ValVT.getSimpleVT(), Offset3,
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LocVT.getSimpleVT(), LocInfo));
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return false;
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}
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