142 lines
3.5 KiB
C++
142 lines
3.5 KiB
C++
//===-- SPUHazardRecognizers.cpp - Cell Hazard Recognizer Impls -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements hazard recognizers for scheduling on Cell SPU
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// processors.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "sched"
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#include "SPUHazardRecognizers.h"
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#include "SPU.h"
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#include "SPUInstrInfo.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Cell SPU hazard recognizer
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//
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// This is the pipeline hazard recognizer for the Cell SPU processor. It does
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// very little right now.
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//===----------------------------------------------------------------------===//
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SPUHazardRecognizer::SPUHazardRecognizer(const TargetInstrInfo &tii) :
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TII(tii),
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EvenOdd(0)
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{
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}
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/// Return the pipeline hazard type encountered or generated by this
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/// instruction. Currently returns NoHazard.
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///
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/// \return NoHazard
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ScheduleHazardRecognizer::HazardType
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SPUHazardRecognizer::getHazardType(SUnit *SU, int Stalls)
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{
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// Initial thoughts on how to do this, but this code cannot work unless the
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// function's prolog and epilog code are also being scheduled so that we can
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// accurately determine which pipeline is being scheduled.
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#if 0
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assert(Stalls == 0 && "SPU hazards don't yet support scoreboard lookahead");
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const SDNode *Node = SU->getNode()->getFlaggedMachineNode();
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ScheduleHazardRecognizer::HazardType retval = NoHazard;
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bool mustBeOdd = false;
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switch (Node->getOpcode()) {
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case SPU::LQDv16i8:
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case SPU::LQDv8i16:
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case SPU::LQDv4i32:
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case SPU::LQDv4f32:
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case SPU::LQDv2f64:
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case SPU::LQDr128:
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case SPU::LQDr64:
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case SPU::LQDr32:
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case SPU::LQDr16:
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case SPU::LQAv16i8:
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case SPU::LQAv8i16:
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case SPU::LQAv4i32:
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case SPU::LQAv4f32:
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case SPU::LQAv2f64:
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case SPU::LQAr128:
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case SPU::LQAr64:
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case SPU::LQAr32:
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case SPU::LQXv4i32:
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case SPU::LQXr128:
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case SPU::LQXr64:
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case SPU::LQXr32:
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case SPU::LQXr16:
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case SPU::STQDv16i8:
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case SPU::STQDv8i16:
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case SPU::STQDv4i32:
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case SPU::STQDv4f32:
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case SPU::STQDv2f64:
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case SPU::STQDr128:
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case SPU::STQDr64:
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case SPU::STQDr32:
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case SPU::STQDr16:
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case SPU::STQDr8:
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case SPU::STQAv16i8:
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case SPU::STQAv8i16:
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case SPU::STQAv4i32:
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case SPU::STQAv4f32:
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case SPU::STQAv2f64:
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case SPU::STQAr128:
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case SPU::STQAr64:
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case SPU::STQAr32:
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case SPU::STQAr16:
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case SPU::STQAr8:
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case SPU::STQXv16i8:
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case SPU::STQXv8i16:
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case SPU::STQXv4i32:
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case SPU::STQXv4f32:
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case SPU::STQXv2f64:
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case SPU::STQXr128:
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case SPU::STQXr64:
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case SPU::STQXr32:
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case SPU::STQXr16:
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case SPU::STQXr8:
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case SPU::RET:
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mustBeOdd = true;
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break;
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default:
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// Assume that this instruction can be on the even pipe
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break;
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}
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if (mustBeOdd && !EvenOdd)
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retval = Hazard;
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DEBUG(errs() << "SPUHazardRecognizer EvenOdd " << EvenOdd << " Hazard "
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<< retval << "\n");
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EvenOdd ^= 1;
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return retval;
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#else
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return NoHazard;
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#endif
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}
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void SPUHazardRecognizer::EmitInstruction(SUnit *SU)
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{
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}
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void SPUHazardRecognizer::AdvanceCycle()
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{
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DEBUG(errs() << "SPUHazardRecognizer::AdvanceCycle\n");
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}
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void SPUHazardRecognizer::EmitNoop()
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{
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AdvanceCycle();
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}
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