251 lines
7.6 KiB
C++
251 lines
7.6 KiB
C++
#ifndef BOOST_ATOMIC_DETAIL_GCC_ARMV6PLUS_HPP
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#define BOOST_ATOMIC_DETAIL_GCC_ARMV6PLUS_HPP
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// Distributed under the Boost Software License, Version 1.0.
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// See accompanying file LICENSE_1_0.txt or copy at
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// http://www.boost.org/LICENSE_1_0.txt)
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//
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// Copyright (c) 2009 Helge Bahmann
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// Copyright (c) 2009 Phil Endecott
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// ARM Code by Phil Endecott, based on other architectures.
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#include <cstddef>
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#include <boost/cstdint.hpp>
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#include <boost/atomic/detail/config.hpp>
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#ifdef BOOST_ATOMIC_HAS_PRAGMA_ONCE
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#pragma once
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#endif
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// From the ARM Architecture Reference Manual for architecture v6:
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//
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// LDREX{<cond>} <Rd>, [<Rn>]
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// <Rd> Specifies the destination register for the memory word addressed by <Rd>
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// <Rn> Specifies the register containing the address.
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//
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// STREX{<cond>} <Rd>, <Rm>, [<Rn>]
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// <Rd> Specifies the destination register for the returned status value.
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// 0 if the operation updates memory
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// 1 if the operation fails to update memory
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// <Rm> Specifies the register containing the word to be stored to memory.
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// <Rn> Specifies the register containing the address.
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// Rd must not be the same register as Rm or Rn.
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//
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// ARM v7 is like ARM v6 plus:
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// There are half-word and byte versions of the LDREX and STREX instructions,
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// LDREXH, LDREXB, STREXH and STREXB.
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// There are also double-word versions, LDREXD and STREXD.
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// (Actually it looks like these are available from version 6k onwards.)
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// FIXME these are not yet used; should be mostly a matter of copy-and-paste.
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// I think you can supply an immediate offset to the address.
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//
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// A memory barrier is effected using a "co-processor 15" instruction,
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// though a separate assembler mnemonic is available for it in v7.
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namespace boost {
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namespace atomics {
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namespace detail {
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// "Thumb 1" is a subset of the ARM instruction set that uses a 16-bit encoding. It
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// doesn't include all instructions and in particular it doesn't include the co-processor
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// instruction used for the memory barrier or the load-locked/store-conditional
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// instructions. So, if we're compiling in "Thumb 1" mode, we need to wrap all of our
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// asm blocks with code to temporarily change to ARM mode.
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//
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// You can only change between ARM and Thumb modes when branching using the bx instruction.
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// bx takes an address specified in a register. The least significant bit of the address
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// indicates the mode, so 1 is added to indicate that the destination code is Thumb.
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// A temporary register is needed for the address and is passed as an argument to these
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// macros. It must be one of the "low" registers accessible to Thumb code, specified
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// using the "l" attribute in the asm statement.
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//
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// Architecture v7 introduces "Thumb 2", which does include (almost?) all of the ARM
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// instruction set. So in v7 we don't need to change to ARM mode; we can write "universal
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// assembler" which will assemble to Thumb 2 or ARM code as appropriate. The only thing
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// we need to do to make this "universal" assembler mode work is to insert "IT" instructions
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// to annotate the conditional instructions. These are ignored in other modes (e.g. v6),
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// so they can always be present.
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#if defined(__thumb__) && !defined(__ARM_ARCH_7A__)
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// FIXME also other v7 variants.
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#define BOOST_ATOMIC_ARM_ASM_START(TMPREG) "adr " #TMPREG ", 1f\n" "bx " #TMPREG "\n" ".arm\n" ".align 4\n" "1: "
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#define BOOST_ATOMIC_ARM_ASM_END(TMPREG) "adr " #TMPREG ", 1f + 1\n" "bx " #TMPREG "\n" ".thumb\n" ".align 2\n" "1: "
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#else
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// The tmpreg is wasted in this case, which is non-optimal.
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#define BOOST_ATOMIC_ARM_ASM_START(TMPREG)
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#define BOOST_ATOMIC_ARM_ASM_END(TMPREG)
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#endif
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#if defined(__ARM_ARCH_7A__)
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// FIXME ditto.
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#define BOOST_ATOMIC_ARM_DMB "dmb\n"
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#else
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#define BOOST_ATOMIC_ARM_DMB "mcr\tp15, 0, r0, c7, c10, 5\n"
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#endif
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inline void
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arm_barrier(void)
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{
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int brtmp;
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__asm__ __volatile__ (
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BOOST_ATOMIC_ARM_ASM_START(%0)
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BOOST_ATOMIC_ARM_DMB
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BOOST_ATOMIC_ARM_ASM_END(%0)
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: "=&l" (brtmp) :: "memory"
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);
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}
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inline void
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platform_fence_before(memory_order order)
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{
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switch(order) {
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case memory_order_release:
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case memory_order_acq_rel:
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case memory_order_seq_cst:
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arm_barrier();
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case memory_order_consume:
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default:;
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}
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}
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inline void
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platform_fence_after(memory_order order)
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{
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switch(order) {
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case memory_order_acquire:
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case memory_order_acq_rel:
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case memory_order_seq_cst:
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arm_barrier();
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default:;
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}
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}
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inline void
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platform_fence_before_store(memory_order order)
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{
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platform_fence_before(order);
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}
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inline void
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platform_fence_after_store(memory_order order)
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{
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if (order == memory_order_seq_cst)
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arm_barrier();
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}
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inline void
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platform_fence_after_load(memory_order order)
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{
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platform_fence_after(order);
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}
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template<typename T>
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inline bool
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platform_cmpxchg32(T & expected, T desired, volatile T * ptr)
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{
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int success;
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int tmp;
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__asm__ (
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BOOST_ATOMIC_ARM_ASM_START(%2)
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"mov %1, #0\n" // success = 0
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"ldrex %0, %3\n" // expected' = *(&i)
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"teq %0, %4\n" // flags = expected'==expected
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"ittt eq\n"
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"strexeq %2, %5, %3\n" // if (flags.equal) *(&i) = desired, tmp = !OK
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"teqeq %2, #0\n" // if (flags.equal) flags = tmp==0
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"moveq %1, #1\n" // if (flags.equal) success = 1
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BOOST_ATOMIC_ARM_ASM_END(%2)
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: "=&r" (expected), // %0
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"=&r" (success), // %1
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"=&l" (tmp), // %2
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"+Q" (*ptr) // %3
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: "r" (expected), // %4
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"r" (desired) // %5
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: "cc"
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);
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return success;
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}
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}
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}
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#define BOOST_ATOMIC_THREAD_FENCE 2
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inline void
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atomic_thread_fence(memory_order order)
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{
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switch(order) {
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case memory_order_acquire:
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case memory_order_release:
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case memory_order_acq_rel:
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case memory_order_seq_cst:
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atomics::detail::arm_barrier();
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default:;
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}
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}
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#define BOOST_ATOMIC_SIGNAL_FENCE 2
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inline void
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atomic_signal_fence(memory_order)
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{
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__asm__ __volatile__ ("" ::: "memory");
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}
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class atomic_flag {
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private:
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atomic_flag(const atomic_flag &) /* = delete */ ;
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atomic_flag & operator=(const atomic_flag &) /* = delete */ ;
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uint32_t v_;
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public:
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atomic_flag(void) : v_(false) {}
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void
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clear(memory_order order = memory_order_seq_cst) volatile
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{
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atomics::detail::platform_fence_before_store(order);
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const_cast<volatile uint32_t &>(v_) = 0;
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atomics::detail::platform_fence_after_store(order);
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}
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bool
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test_and_set(memory_order order = memory_order_seq_cst) volatile
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{
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atomics::detail::platform_fence_before(order);
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uint32_t expected = v_;
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do {
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if (expected == 1)
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break;
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} while (!atomics::detail::platform_cmpxchg32(expected, (uint32_t)1, &v_));
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atomics::detail::platform_fence_after(order);
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return expected;
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}
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};
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#define BOOST_ATOMIC_FLAG_LOCK_FREE 2
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}
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#undef BOOST_ATOMIC_ARM_ASM_START
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#undef BOOST_ATOMIC_ARM_ASM_END
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#include <boost/atomic/detail/base.hpp>
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#if !defined(BOOST_ATOMIC_FORCE_FALLBACK)
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#define BOOST_ATOMIC_CHAR_LOCK_FREE 2
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#define BOOST_ATOMIC_CHAR16_T_LOCK_FREE 2
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#define BOOST_ATOMIC_CHAR32_T_LOCK_FREE 2
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#define BOOST_ATOMIC_WCHAR_T_LOCK_FREE 2
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#define BOOST_ATOMIC_SHORT_LOCK_FREE 2
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#define BOOST_ATOMIC_INT_LOCK_FREE 2
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#define BOOST_ATOMIC_LONG_LOCK_FREE 2
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#define BOOST_ATOMIC_LLONG_LOCK_FREE 0
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#define BOOST_ATOMIC_POINTER_LOCK_FREE 2
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#define BOOST_ATOMIC_BOOL_LOCK_FREE 2
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#include <boost/atomic/detail/cas32weak.hpp>
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#endif /* !defined(BOOST_ATOMIC_FORCE_FALLBACK) */
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#endif
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