2851 lines
73 KiB
C++
2851 lines
73 KiB
C++
#ifndef BOOST_ATOMIC_DETAIL_GCC_PPC_HPP
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#define BOOST_ATOMIC_DETAIL_GCC_PPC_HPP
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// Copyright (c) 2009 Helge Bahmann
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// Copyright (c) 2013 Tim Blechmann
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//
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// Distributed under the Boost Software License, Version 1.0.
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// See accompanying file LICENSE_1_0.txt or copy at
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// http://www.boost.org/LICENSE_1_0.txt)
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#include <cstddef>
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#include <boost/cstdint.hpp>
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#include <boost/atomic/detail/config.hpp>
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#ifdef BOOST_ATOMIC_HAS_PRAGMA_ONCE
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#pragma once
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#endif
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/*
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Refer to: Motorola: "Programming Environments Manual for 32-Bit
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Implementations of the PowerPC Architecture", Appendix E:
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"Synchronization Programming Examples" for an explanation of what is
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going on here (can be found on the web at various places by the
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name "MPCFPE32B.pdf", Google is your friend...)
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Most of the atomic operations map to instructions in a relatively
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straight-forward fashion, but "load"s may at first glance appear
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a bit strange as they map to:
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lwz %rX, addr
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cmpw %rX, %rX
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bne- 1f
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1:
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That is, the CPU is forced to perform a branch that "formally" depends
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on the value retrieved from memory. This scheme has an overhead of
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about 1-2 clock cycles per load, but it allows to map "acquire" to
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the "isync" instruction instead of "sync" uniformly and for all type
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of atomic operations. Since "isync" has a cost of about 15 clock
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cycles, while "sync" hast a cost of about 50 clock cycles, the small
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penalty to atomic loads more than compensates for this.
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Byte- and halfword-sized atomic values are realized by encoding the
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value to be represented into a word, performing sign/zero extension
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as appropriate. This means that after add/sub operations the value
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needs fixing up to accurately preserve the wrap-around semantic of
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the smaller type. (Nothing special needs to be done for the bit-wise
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and the "exchange type" operators as the compiler already sees to
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it that values carried in registers are extended appropriately and
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everything falls into place naturally).
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The register constraint "b" instructs gcc to use any register
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except r0; this is sometimes required because the encoding for
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r0 is used to signify "constant zero" in a number of instructions,
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making r0 unusable in this place. For simplicity this constraint
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is used everywhere since I am to lazy to look this up on a
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per-instruction basis, and ppc has enough registers for this not
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to pose a problem.
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*/
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namespace boost {
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namespace atomics {
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namespace detail {
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inline void
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ppc_fence_before(memory_order order)
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{
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switch(order) {
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case memory_order_release:
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case memory_order_acq_rel:
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#if defined(__powerpc64__)
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__asm__ __volatile__ ("lwsync" ::: "memory");
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break;
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#endif
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case memory_order_seq_cst:
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__asm__ __volatile__ ("sync" ::: "memory");
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default:;
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}
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}
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inline void
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ppc_fence_after(memory_order order)
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{
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switch(order) {
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case memory_order_acquire:
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case memory_order_acq_rel:
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case memory_order_seq_cst:
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__asm__ __volatile__ ("isync");
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case memory_order_consume:
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__asm__ __volatile__ ("" ::: "memory");
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default:;
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}
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}
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inline void
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ppc_fence_after_store(memory_order order)
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{
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switch(order) {
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case memory_order_seq_cst:
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__asm__ __volatile__ ("sync");
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default:;
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}
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}
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}
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}
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class atomic_flag
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{
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private:
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atomic_flag(const atomic_flag &) /* = delete */ ;
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atomic_flag & operator=(const atomic_flag &) /* = delete */ ;
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uint32_t v_;
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public:
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BOOST_CONSTEXPR atomic_flag(void) BOOST_NOEXCEPT : v_(0) {}
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void
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clear(memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
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{
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atomics::detail::ppc_fence_before(order);
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const_cast<volatile uint32_t &>(v_) = 0;
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atomics::detail::ppc_fence_after_store(order);
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}
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bool
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test_and_set(memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
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{
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uint32_t original;
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atomics::detail::ppc_fence_before(order);
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__asm__ (
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"1:\n"
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"lwarx %0,%y1\n"
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"stwcx. %2,%y1\n"
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"bne- 1b\n"
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: "=&b" (original), "+Z"(v_)
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: "b" (1)
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: "cr0"
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);
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atomics::detail::ppc_fence_after(order);
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return original;
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}
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};
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} /* namespace boost */
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#define BOOST_ATOMIC_FLAG_LOCK_FREE 2
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#include <boost/atomic/detail/base.hpp>
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#if !defined(BOOST_ATOMIC_FORCE_FALLBACK)
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#define BOOST_ATOMIC_CHAR_LOCK_FREE 2
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#define BOOST_ATOMIC_CHAR16_T_LOCK_FREE 2
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#define BOOST_ATOMIC_CHAR32_T_LOCK_FREE 2
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#define BOOST_ATOMIC_WCHAR_T_LOCK_FREE 2
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#define BOOST_ATOMIC_SHORT_LOCK_FREE 2
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#define BOOST_ATOMIC_INT_LOCK_FREE 2
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#define BOOST_ATOMIC_LONG_LOCK_FREE 2
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#define BOOST_ATOMIC_POINTER_LOCK_FREE 2
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#if defined(__powerpc64__)
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#define BOOST_ATOMIC_LLONG_LOCK_FREE 2
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#else
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#define BOOST_ATOMIC_LLONG_LOCK_FREE 0
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#endif
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#define BOOST_ATOMIC_BOOL_LOCK_FREE 2
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/* Would like to move the slow-path of failed compare_exchange
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(that clears the "success" bit) out-of-line. gcc can in
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principle do that using ".subsection"/".previous", but Apple's
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binutils seemingly does not understand that. Therefore wrap
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the "clear" of the flag in a macro and let it remain
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in-line for Apple
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*/
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#if !defined(__APPLE__)
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#define BOOST_ATOMIC_ASM_SLOWPATH_CLEAR \
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"9:\n" \
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".subsection 2\n" \
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"2: addi %1,0,0\n" \
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"b 9b\n" \
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".previous\n" \
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#else
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#define BOOST_ATOMIC_ASM_SLOWPATH_CLEAR \
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"b 9f\n" \
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"2: addi %1,0,0\n" \
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"9:\n" \
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#endif
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namespace boost {
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namespace atomics {
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namespace detail {
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/* integral types */
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template<typename T>
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class base_atomic<T, int, 1, true>
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{
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typedef base_atomic this_type;
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typedef T value_type;
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typedef int32_t storage_type;
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typedef T difference_type;
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public:
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BOOST_CONSTEXPR explicit base_atomic(value_type v) BOOST_NOEXCEPT : v_(v) {}
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base_atomic(void) {}
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void
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store(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
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{
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ppc_fence_before(order);
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__asm__ (
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"stw %1, %0\n"
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: "+m"(v_)
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: "r" (v)
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);
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ppc_fence_after_store(order);
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}
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value_type
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load(memory_order order = memory_order_seq_cst) const volatile BOOST_NOEXCEPT
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{
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value_type v;
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__asm__ __volatile__ (
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"lwz %0, %1\n"
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"cmpw %0, %0\n"
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"bne- 1f\n"
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"1:\n"
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: "=&r" (v)
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: "m" (v_)
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);
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ppc_fence_after(order);
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return v;
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}
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value_type
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exchange(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
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{
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value_type original;
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ppc_fence_before(order);
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__asm__ (
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"1:\n"
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"lwarx %0,%y1\n"
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"stwcx. %2,%y1\n"
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"bne- 1b\n"
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: "=&b" (original), "+Z"(v_)
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: "b" (v)
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: "cr0"
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);
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ppc_fence_after(order);
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return original;
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}
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bool
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compare_exchange_weak(
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value_type & expected,
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value_type desired,
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memory_order success_order,
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memory_order failure_order) volatile BOOST_NOEXCEPT
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{
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int success;
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ppc_fence_before(success_order);
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__asm__(
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"lwarx %0,%y2\n"
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"cmpw %0, %3\n"
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"bne- 2f\n"
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"stwcx. %4,%y2\n"
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"bne- 2f\n"
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"addi %1,0,1\n"
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"1:"
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BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
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: "=&b" (expected), "=&b" (success), "+Z"(v_)
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: "b" (expected), "b" (desired)
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: "cr0"
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);
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if (success)
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ppc_fence_after(success_order);
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else
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ppc_fence_after(failure_order);
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return success;
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}
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bool
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compare_exchange_strong(
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value_type & expected,
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value_type desired,
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memory_order success_order,
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memory_order failure_order) volatile BOOST_NOEXCEPT
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{
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int success;
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ppc_fence_before(success_order);
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__asm__(
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"0: lwarx %0,%y2\n"
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"cmpw %0, %3\n"
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"bne- 2f\n"
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"stwcx. %4,%y2\n"
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"bne- 0b\n"
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"addi %1,0,1\n"
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"1:"
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BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
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: "=&b" (expected), "=&b" (success), "+Z"(v_)
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: "b" (expected), "b" (desired)
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: "cr0"
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);
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if (success)
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ppc_fence_after(success_order);
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else
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ppc_fence_after(failure_order);
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return success;
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}
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value_type
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fetch_add(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
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{
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value_type original, tmp;
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ppc_fence_before(order);
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__asm__ (
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"1:\n"
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"lwarx %0,%y2\n"
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"add %1,%0,%3\n"
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"extsb %1, %1\n"
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"stwcx. %1,%y2\n"
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"bne- 1b\n"
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: "=&b" (original), "=&b" (tmp), "+Z"(v_)
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: "b" (v)
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: "cc");
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ppc_fence_after(order);
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return original;
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}
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value_type
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fetch_sub(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
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{
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value_type original, tmp;
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ppc_fence_before(order);
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__asm__ (
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"1:\n"
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"lwarx %0,%y2\n"
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"sub %1,%0,%3\n"
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"extsb %1, %1\n"
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"stwcx. %1,%y2\n"
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"bne- 1b\n"
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: "=&b" (original), "=&b" (tmp), "+Z"(v_)
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: "b" (v)
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: "cc");
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ppc_fence_after(order);
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return original;
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}
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value_type
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fetch_and(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
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{
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value_type original, tmp;
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ppc_fence_before(order);
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__asm__ (
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"1:\n"
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"lwarx %0,%y2\n"
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"and %1,%0,%3\n"
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"stwcx. %1,%y2\n"
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"bne- 1b\n"
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: "=&b" (original), "=&b" (tmp), "+Z"(v_)
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: "b" (v)
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: "cc");
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ppc_fence_after(order);
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return original;
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}
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value_type
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fetch_or(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
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{
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value_type original, tmp;
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ppc_fence_before(order);
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__asm__ (
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"1:\n"
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"lwarx %0,%y2\n"
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"or %1,%0,%3\n"
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"stwcx. %1,%y2\n"
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"bne- 1b\n"
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: "=&b" (original), "=&b" (tmp), "+Z"(v_)
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: "b" (v)
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: "cc");
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ppc_fence_after(order);
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return original;
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}
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value_type
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fetch_xor(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
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{
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value_type original, tmp;
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ppc_fence_before(order);
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__asm__ (
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"1:\n"
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"lwarx %0,%y2\n"
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"xor %1,%0,%3\n"
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"stwcx. %1,%y2\n"
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"bne- 1b\n"
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: "=&b" (original), "=&b" (tmp), "+Z"(v_)
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: "b" (v)
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: "cc");
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ppc_fence_after(order);
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return original;
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}
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bool
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is_lock_free(void) const volatile BOOST_NOEXCEPT
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{
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return true;
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}
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BOOST_ATOMIC_DECLARE_INTEGRAL_OPERATORS
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private:
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base_atomic(const base_atomic &) /* = delete */ ;
|
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void operator=(const base_atomic &) /* = delete */ ;
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storage_type v_;
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};
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template<typename T>
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class base_atomic<T, int, 1, false>
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{
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typedef base_atomic this_type;
|
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typedef T value_type;
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typedef uint32_t storage_type;
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typedef T difference_type;
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public:
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BOOST_CONSTEXPR explicit base_atomic(value_type v) BOOST_NOEXCEPT : v_(v) {}
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base_atomic(void) {}
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|
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void
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store(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
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{
|
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ppc_fence_before(order);
|
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__asm__ (
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"stw %1, %0\n"
|
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: "+m"(v_)
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: "r" (v)
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);
|
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ppc_fence_after_store(order);
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}
|
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|
|
value_type
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load(memory_order order = memory_order_seq_cst) const volatile BOOST_NOEXCEPT
|
|
{
|
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value_type v;
|
|
__asm__ __volatile__ (
|
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"lwz %0, %1\n"
|
|
"cmpw %0, %0\n"
|
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"bne- 1f\n"
|
|
"1:\n"
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: "=&r" (v)
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|
: "m" (v_)
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);
|
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ppc_fence_after(order);
|
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return v;
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|
}
|
|
|
|
value_type
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exchange(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y1\n"
|
|
"stwcx. %2,%y1\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "+Z"(v_)
|
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: "b" (v)
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: "cr0"
|
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);
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_weak(
|
|
value_type & expected,
|
|
value_type desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"lwarx %0,%y2\n"
|
|
"cmpw %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stwcx. %4,%y2\n"
|
|
"bne- 2f\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected), "b" (desired)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
return success;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_strong(
|
|
value_type & expected,
|
|
value_type desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"0: lwarx %0,%y2\n"
|
|
"cmpw %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stwcx. %4,%y2\n"
|
|
"bne- 0b\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected), "b" (desired)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
return success;
|
|
}
|
|
|
|
value_type
|
|
fetch_add(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y2\n"
|
|
"add %1,%0,%3\n"
|
|
"rlwinm %1, %1, 0, 0xff\n"
|
|
"stwcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
value_type
|
|
fetch_sub(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y2\n"
|
|
"sub %1,%0,%3\n"
|
|
"rlwinm %1, %1, 0, 0xff\n"
|
|
"stwcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
value_type
|
|
fetch_and(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y2\n"
|
|
"and %1,%0,%3\n"
|
|
"stwcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
value_type
|
|
fetch_or(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y2\n"
|
|
"or %1,%0,%3\n"
|
|
"stwcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
value_type
|
|
fetch_xor(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y2\n"
|
|
"xor %1,%0,%3\n"
|
|
"stwcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
bool
|
|
is_lock_free(void) const volatile BOOST_NOEXCEPT
|
|
{
|
|
return true;
|
|
}
|
|
|
|
BOOST_ATOMIC_DECLARE_INTEGRAL_OPERATORS
|
|
private:
|
|
base_atomic(const base_atomic &) /* = delete */ ;
|
|
void operator=(const base_atomic &) /* = delete */ ;
|
|
storage_type v_;
|
|
};
|
|
|
|
template<typename T>
|
|
class base_atomic<T, int, 2, true>
|
|
{
|
|
typedef base_atomic this_type;
|
|
typedef T value_type;
|
|
typedef int32_t storage_type;
|
|
typedef T difference_type;
|
|
public:
|
|
BOOST_CONSTEXPR explicit base_atomic(value_type v) BOOST_NOEXCEPT : v_(v) {}
|
|
base_atomic(void) {}
|
|
|
|
void
|
|
store(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"stw %1, %0\n"
|
|
: "+m"(v_)
|
|
: "r" (v)
|
|
);
|
|
ppc_fence_after_store(order);
|
|
}
|
|
|
|
value_type
|
|
load(memory_order order = memory_order_seq_cst) const volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type v;
|
|
__asm__ __volatile__ (
|
|
"lwz %0, %1\n"
|
|
"cmpw %0, %0\n"
|
|
"bne- 1f\n"
|
|
"1:\n"
|
|
: "=&r" (v)
|
|
: "m" (v_)
|
|
);
|
|
ppc_fence_after(order);
|
|
return v;
|
|
}
|
|
|
|
value_type
|
|
exchange(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y1\n"
|
|
"stwcx. %2,%y1\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cr0"
|
|
);
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_weak(
|
|
value_type & expected,
|
|
value_type desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"lwarx %0,%y2\n"
|
|
"cmpw %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stwcx. %4,%y2\n"
|
|
"bne- 2f\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected), "b" (desired)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
return success;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_strong(
|
|
value_type & expected,
|
|
value_type desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"0: lwarx %0,%y2\n"
|
|
"cmpw %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stwcx. %4,%y2\n"
|
|
"bne- 0b\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected), "b" (desired)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
return success;
|
|
}
|
|
|
|
value_type
|
|
fetch_add(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y2\n"
|
|
"add %1,%0,%3\n"
|
|
"extsh %1, %1\n"
|
|
"stwcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
value_type
|
|
fetch_sub(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y2\n"
|
|
"sub %1,%0,%3\n"
|
|
"extsh %1, %1\n"
|
|
"stwcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
value_type
|
|
fetch_and(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y2\n"
|
|
"and %1,%0,%3\n"
|
|
"stwcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
value_type
|
|
fetch_or(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y2\n"
|
|
"or %1,%0,%3\n"
|
|
"stwcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
value_type
|
|
fetch_xor(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y2\n"
|
|
"xor %1,%0,%3\n"
|
|
"stwcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
bool
|
|
is_lock_free(void) const volatile BOOST_NOEXCEPT
|
|
{
|
|
return true;
|
|
}
|
|
|
|
BOOST_ATOMIC_DECLARE_INTEGRAL_OPERATORS
|
|
private:
|
|
base_atomic(const base_atomic &) /* = delete */ ;
|
|
void operator=(const base_atomic &) /* = delete */ ;
|
|
storage_type v_;
|
|
};
|
|
|
|
template<typename T>
|
|
class base_atomic<T, int, 2, false>
|
|
{
|
|
typedef base_atomic this_type;
|
|
typedef T value_type;
|
|
typedef uint32_t storage_type;
|
|
typedef T difference_type;
|
|
public:
|
|
BOOST_CONSTEXPR explicit base_atomic(value_type v) BOOST_NOEXCEPT : v_(v) {}
|
|
base_atomic(void) {}
|
|
|
|
void
|
|
store(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"stw %1, %0\n"
|
|
: "+m"(v_)
|
|
: "r" (v)
|
|
);
|
|
ppc_fence_after_store(order);
|
|
}
|
|
|
|
value_type
|
|
load(memory_order order = memory_order_seq_cst) const volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type v;
|
|
__asm__ __volatile__ (
|
|
"lwz %0, %1\n"
|
|
"cmpw %0, %0\n"
|
|
"bne- 1f\n"
|
|
"1:\n"
|
|
: "=&r" (v)
|
|
: "m" (v_)
|
|
);
|
|
ppc_fence_after(order);
|
|
return v;
|
|
}
|
|
|
|
value_type
|
|
exchange(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y1\n"
|
|
"stwcx. %2,%y1\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cr0"
|
|
);
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_weak(
|
|
value_type & expected,
|
|
value_type desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"lwarx %0,%y2\n"
|
|
"cmpw %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stwcx. %4,%y2\n"
|
|
"bne- 2f\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected), "b" (desired)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
return success;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_strong(
|
|
value_type & expected,
|
|
value_type desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"0: lwarx %0,%y2\n"
|
|
"cmpw %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stwcx. %4,%y2\n"
|
|
"bne- 0b\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected), "b" (desired)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
return success;
|
|
}
|
|
|
|
value_type
|
|
fetch_add(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y2\n"
|
|
"add %1,%0,%3\n"
|
|
"rlwinm %1, %1, 0, 0xffff\n"
|
|
"stwcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
value_type
|
|
fetch_sub(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y2\n"
|
|
"sub %1,%0,%3\n"
|
|
"rlwinm %1, %1, 0, 0xffff\n"
|
|
"stwcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
value_type
|
|
fetch_and(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y2\n"
|
|
"and %1,%0,%3\n"
|
|
"stwcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
value_type
|
|
fetch_or(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y2\n"
|
|
"or %1,%0,%3\n"
|
|
"stwcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
value_type
|
|
fetch_xor(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y2\n"
|
|
"xor %1,%0,%3\n"
|
|
"stwcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
bool
|
|
is_lock_free(void) const volatile BOOST_NOEXCEPT
|
|
{
|
|
return true;
|
|
}
|
|
|
|
BOOST_ATOMIC_DECLARE_INTEGRAL_OPERATORS
|
|
private:
|
|
base_atomic(const base_atomic &) /* = delete */ ;
|
|
void operator=(const base_atomic &) /* = delete */ ;
|
|
storage_type v_;
|
|
};
|
|
|
|
template<typename T, bool Sign>
|
|
class base_atomic<T, int, 4, Sign>
|
|
{
|
|
typedef base_atomic this_type;
|
|
typedef T value_type;
|
|
typedef T difference_type;
|
|
public:
|
|
BOOST_CONSTEXPR explicit base_atomic(value_type v) BOOST_NOEXCEPT : v_(v) {}
|
|
base_atomic(void) {}
|
|
|
|
void
|
|
store(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
ppc_fence_before(order);
|
|
const_cast<volatile value_type &>(v_) = v;
|
|
ppc_fence_after_store(order);
|
|
}
|
|
|
|
value_type
|
|
load(memory_order order = memory_order_seq_cst) const volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type v = const_cast<const volatile value_type &>(v_);
|
|
__asm__ __volatile__ (
|
|
"cmpw %0, %0\n"
|
|
"bne- 1f\n"
|
|
"1:\n"
|
|
: "+b"(v)
|
|
:
|
|
: "cr0"
|
|
);
|
|
ppc_fence_after(order);
|
|
return v;
|
|
}
|
|
|
|
value_type
|
|
exchange(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y1\n"
|
|
"stwcx. %2,%y1\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cr0"
|
|
);
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_weak(
|
|
value_type & expected,
|
|
value_type desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"lwarx %0,%y2\n"
|
|
"cmpw %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stwcx. %4,%y2\n"
|
|
"bne- 2f\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected), "b" (desired)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
return success;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_strong(
|
|
value_type & expected,
|
|
value_type desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"0: lwarx %0,%y2\n"
|
|
"cmpw %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stwcx. %4,%y2\n"
|
|
"bne- 0b\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected), "b" (desired)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
return success;
|
|
}
|
|
|
|
value_type
|
|
fetch_add(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y2\n"
|
|
"add %1,%0,%3\n"
|
|
"stwcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
value_type
|
|
fetch_sub(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y2\n"
|
|
"sub %1,%0,%3\n"
|
|
"stwcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
value_type
|
|
fetch_and(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y2\n"
|
|
"and %1,%0,%3\n"
|
|
"stwcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
value_type
|
|
fetch_or(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y2\n"
|
|
"or %1,%0,%3\n"
|
|
"stwcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
value_type
|
|
fetch_xor(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y2\n"
|
|
"xor %1,%0,%3\n"
|
|
"stwcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
bool
|
|
is_lock_free(void) const volatile BOOST_NOEXCEPT
|
|
{
|
|
return true;
|
|
}
|
|
|
|
BOOST_ATOMIC_DECLARE_INTEGRAL_OPERATORS
|
|
private:
|
|
base_atomic(const base_atomic &) /* = delete */ ;
|
|
void operator=(const base_atomic &) /* = delete */ ;
|
|
value_type v_;
|
|
};
|
|
|
|
#if defined(__powerpc64__)
|
|
|
|
template<typename T, bool Sign>
|
|
class base_atomic<T, int, 8, Sign>
|
|
{
|
|
typedef base_atomic this_type;
|
|
typedef T value_type;
|
|
typedef T difference_type;
|
|
public:
|
|
BOOST_CONSTEXPR explicit base_atomic(value_type v) BOOST_NOEXCEPT : v_(v) {}
|
|
base_atomic(void) {}
|
|
|
|
void
|
|
store(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
ppc_fence_before(order);
|
|
const_cast<volatile value_type &>(v_) = v;
|
|
ppc_fence_after_store(order);
|
|
}
|
|
|
|
value_type
|
|
load(memory_order order = memory_order_seq_cst) const volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type v = const_cast<const volatile value_type &>(v_);
|
|
__asm__ __volatile__ (
|
|
"cmpd %0, %0\n"
|
|
"bne- 1f\n"
|
|
"1:\n"
|
|
: "+b"(v)
|
|
:
|
|
: "cr0"
|
|
);
|
|
ppc_fence_after(order);
|
|
return v;
|
|
}
|
|
|
|
value_type
|
|
exchange(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"ldarx %0,%y1\n"
|
|
"stdcx. %2,%y1\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cr0"
|
|
);
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_weak(
|
|
value_type & expected,
|
|
value_type desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"ldarx %0,%y2\n"
|
|
"cmpd %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stdcx. %4,%y2\n"
|
|
"bne- 2f\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected), "b" (desired)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
return success;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_strong(
|
|
value_type & expected,
|
|
value_type desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"0: ldarx %0,%y2\n"
|
|
"cmpd %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stdcx. %4,%y2\n"
|
|
"bne- 0b\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected), "b" (desired)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
return success;
|
|
}
|
|
|
|
value_type
|
|
fetch_add(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"ldarx %0,%y2\n"
|
|
"add %1,%0,%3\n"
|
|
"stdcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
value_type
|
|
fetch_sub(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"ldarx %0,%y2\n"
|
|
"sub %1,%0,%3\n"
|
|
"stdcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
value_type
|
|
fetch_and(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"ldarx %0,%y2\n"
|
|
"and %1,%0,%3\n"
|
|
"stdcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
value_type
|
|
fetch_or(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"ldarx %0,%y2\n"
|
|
"or %1,%0,%3\n"
|
|
"stdcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
value_type
|
|
fetch_xor(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"ldarx %0,%y2\n"
|
|
"xor %1,%0,%3\n"
|
|
"stdcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
bool
|
|
is_lock_free(void) const volatile BOOST_NOEXCEPT
|
|
{
|
|
return true;
|
|
}
|
|
|
|
BOOST_ATOMIC_DECLARE_INTEGRAL_OPERATORS
|
|
private:
|
|
base_atomic(const base_atomic &) /* = delete */ ;
|
|
void operator=(const base_atomic &) /* = delete */ ;
|
|
value_type v_;
|
|
};
|
|
|
|
#endif
|
|
|
|
/* pointer types */
|
|
|
|
#if !defined(__powerpc64__)
|
|
|
|
template<bool Sign>
|
|
class base_atomic<void *, void *, 4, Sign>
|
|
{
|
|
typedef base_atomic this_type;
|
|
typedef ptrdiff_t difference_type;
|
|
typedef void * value_type;
|
|
public:
|
|
BOOST_CONSTEXPR explicit base_atomic(value_type v) BOOST_NOEXCEPT : v_(v) {}
|
|
base_atomic(void) {}
|
|
|
|
void
|
|
store(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"stw %1, %0\n"
|
|
: "+m" (v_)
|
|
: "r" (v)
|
|
);
|
|
ppc_fence_after_store(order);
|
|
}
|
|
|
|
value_type
|
|
load(memory_order order = memory_order_seq_cst) const volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type v;
|
|
__asm__ (
|
|
"lwz %0, %1\n"
|
|
"cmpw %0, %0\n"
|
|
"bne- 1f\n"
|
|
"1:\n"
|
|
: "=r"(v)
|
|
: "m"(v_)
|
|
: "cr0"
|
|
);
|
|
ppc_fence_after(order);
|
|
return v;
|
|
}
|
|
|
|
value_type
|
|
exchange(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y1\n"
|
|
"stwcx. %2,%y1\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cr0"
|
|
);
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_weak(
|
|
value_type & expected,
|
|
value_type desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"lwarx %0,%y2\n"
|
|
"cmpw %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stwcx. %4,%y2\n"
|
|
"bne- 2f\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected), "b" (desired)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
return success;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_strong(
|
|
value_type & expected,
|
|
value_type desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"0: lwarx %0,%y2\n"
|
|
"cmpw %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stwcx. %4,%y2\n"
|
|
"bne- 0b\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected), "b" (desired)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
return success;
|
|
}
|
|
|
|
bool
|
|
is_lock_free(void) const volatile BOOST_NOEXCEPT
|
|
{
|
|
return true;
|
|
}
|
|
|
|
value_type
|
|
fetch_add(difference_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y2\n"
|
|
"add %1,%0,%3\n"
|
|
"stwcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
value_type
|
|
fetch_sub(difference_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y2\n"
|
|
"sub %1,%0,%3\n"
|
|
"stwcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
BOOST_ATOMIC_DECLARE_VOID_POINTER_OPERATORS
|
|
private:
|
|
base_atomic(const base_atomic &) /* = delete */ ;
|
|
void operator=(const base_atomic &) /* = delete */ ;
|
|
value_type v_;
|
|
};
|
|
|
|
template<typename T, bool Sign>
|
|
class base_atomic<T *, void *, 4, Sign>
|
|
{
|
|
typedef base_atomic this_type;
|
|
typedef T * value_type;
|
|
typedef ptrdiff_t difference_type;
|
|
public:
|
|
BOOST_CONSTEXPR explicit base_atomic(value_type v) BOOST_NOEXCEPT : v_(v) {}
|
|
base_atomic(void) {}
|
|
|
|
void
|
|
store(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"stw %1, %0\n"
|
|
: "+m" (v_)
|
|
: "r" (v)
|
|
);
|
|
ppc_fence_after_store(order);
|
|
}
|
|
|
|
value_type
|
|
load(memory_order order = memory_order_seq_cst) const volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type v;
|
|
__asm__ (
|
|
"lwz %0, %1\n"
|
|
"cmpw %0, %0\n"
|
|
"bne- 1f\n"
|
|
"1:\n"
|
|
: "=r"(v)
|
|
: "m"(v_)
|
|
: "cr0"
|
|
);
|
|
ppc_fence_after(order);
|
|
return v;
|
|
}
|
|
|
|
value_type
|
|
exchange(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y1\n"
|
|
"stwcx. %2,%y1\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cr0"
|
|
);
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_weak(
|
|
value_type & expected,
|
|
value_type desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"lwarx %0,%y2\n"
|
|
"cmpw %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stwcx. %4,%y2\n"
|
|
"bne- 2f\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected), "b" (desired)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
return success;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_strong(
|
|
value_type & expected,
|
|
value_type desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"0: lwarx %0,%y2\n"
|
|
"cmpw %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stwcx. %4,%y2\n"
|
|
"bne- 0b\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected), "b" (desired)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
return success;
|
|
}
|
|
|
|
value_type
|
|
fetch_add(difference_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
v = v * sizeof(*v_);
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y2\n"
|
|
"add %1,%0,%3\n"
|
|
"stwcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
value_type
|
|
fetch_sub(difference_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
v = v * sizeof(*v_);
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y2\n"
|
|
"sub %1,%0,%3\n"
|
|
"stwcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
bool
|
|
is_lock_free(void) const volatile BOOST_NOEXCEPT
|
|
{
|
|
return true;
|
|
}
|
|
|
|
BOOST_ATOMIC_DECLARE_POINTER_OPERATORS
|
|
private:
|
|
base_atomic(const base_atomic &) /* = delete */ ;
|
|
void operator=(const base_atomic &) /* = delete */ ;
|
|
value_type v_;
|
|
};
|
|
|
|
#else
|
|
|
|
template<bool Sign>
|
|
class base_atomic<void *, void *, 8, Sign>
|
|
{
|
|
typedef base_atomic this_type;
|
|
typedef ptrdiff_t difference_type;
|
|
typedef void * value_type;
|
|
public:
|
|
BOOST_CONSTEXPR explicit base_atomic(value_type v) BOOST_NOEXCEPT : v_(v) {}
|
|
base_atomic(void) {}
|
|
|
|
void
|
|
store(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"std %1, %0\n"
|
|
: "+m" (v_)
|
|
: "r" (v)
|
|
);
|
|
ppc_fence_after_store(order);
|
|
}
|
|
|
|
value_type
|
|
load(memory_order order = memory_order_seq_cst) const volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type v;
|
|
__asm__ (
|
|
"ld %0, %1\n"
|
|
"cmpd %0, %0\n"
|
|
"bne- 1f\n"
|
|
"1:\n"
|
|
: "=r"(v)
|
|
: "m"(v_)
|
|
: "cr0"
|
|
);
|
|
ppc_fence_after(order);
|
|
return v;
|
|
}
|
|
|
|
value_type
|
|
exchange(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"ldarx %0,%y1\n"
|
|
"stdcx. %2,%y1\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cr0"
|
|
);
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_weak(
|
|
value_type & expected,
|
|
value_type desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"ldarx %0,%y2\n"
|
|
"cmpd %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stdcx. %4,%y2\n"
|
|
"bne- 2f\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected), "b" (desired)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
return success;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_strong(
|
|
value_type & expected,
|
|
value_type desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"0: ldarx %0,%y2\n"
|
|
"cmpd %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stdcx. %4,%y2\n"
|
|
"bne- 0b\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected), "b" (desired)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
return success;
|
|
}
|
|
|
|
bool
|
|
is_lock_free(void) const volatile BOOST_NOEXCEPT
|
|
{
|
|
return true;
|
|
}
|
|
|
|
value_type
|
|
fetch_add(difference_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"ldarx %0,%y2\n"
|
|
"add %1,%0,%3\n"
|
|
"stdcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
value_type
|
|
fetch_sub(difference_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"ldarx %0,%y2\n"
|
|
"sub %1,%0,%3\n"
|
|
"stdcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
BOOST_ATOMIC_DECLARE_VOID_POINTER_OPERATORS
|
|
private:
|
|
base_atomic(const base_atomic &) /* = delete */ ;
|
|
void operator=(const base_atomic &) /* = delete */ ;
|
|
value_type v_;
|
|
};
|
|
|
|
template<typename T, bool Sign>
|
|
class base_atomic<T *, void *, 8, Sign>
|
|
{
|
|
typedef base_atomic this_type;
|
|
typedef T * value_type;
|
|
typedef ptrdiff_t difference_type;
|
|
public:
|
|
BOOST_CONSTEXPR explicit base_atomic(value_type v) BOOST_NOEXCEPT : v_(v) {}
|
|
base_atomic(void) {}
|
|
|
|
void
|
|
store(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"std %1, %0\n"
|
|
: "+m" (v_)
|
|
: "r" (v)
|
|
);
|
|
ppc_fence_after_store(order);
|
|
}
|
|
|
|
value_type
|
|
load(memory_order order = memory_order_seq_cst) const volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type v;
|
|
__asm__ (
|
|
"ld %0, %1\n"
|
|
"cmpd %0, %0\n"
|
|
"bne- 1f\n"
|
|
"1:\n"
|
|
: "=r"(v)
|
|
: "m"(v_)
|
|
: "cr0"
|
|
);
|
|
ppc_fence_after(order);
|
|
return v;
|
|
}
|
|
|
|
value_type
|
|
exchange(value_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
value_type original;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"ldarx %0,%y1\n"
|
|
"stdcx. %2,%y1\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cr0"
|
|
);
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_weak(
|
|
value_type & expected,
|
|
value_type desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"ldarx %0,%y2\n"
|
|
"cmpd %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stdcx. %4,%y2\n"
|
|
"bne- 2f\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected), "b" (desired)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
return success;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_strong(
|
|
value_type & expected,
|
|
value_type desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"0: ldarx %0,%y2\n"
|
|
"cmpd %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stdcx. %4,%y2\n"
|
|
"bne- 0b\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected), "b" (desired)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
return success;
|
|
}
|
|
|
|
value_type
|
|
fetch_add(difference_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
v = v * sizeof(*v_);
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"ldarx %0,%y2\n"
|
|
"add %1,%0,%3\n"
|
|
"stdcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
value_type
|
|
fetch_sub(difference_type v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
v = v * sizeof(*v_);
|
|
value_type original, tmp;
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"ldarx %0,%y2\n"
|
|
"sub %1,%0,%3\n"
|
|
"stdcx. %1,%y2\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "=&b" (tmp), "+Z"(v_)
|
|
: "b" (v)
|
|
: "cc");
|
|
ppc_fence_after(order);
|
|
return original;
|
|
}
|
|
|
|
bool
|
|
is_lock_free(void) const volatile BOOST_NOEXCEPT
|
|
{
|
|
return true;
|
|
}
|
|
|
|
BOOST_ATOMIC_DECLARE_POINTER_OPERATORS
|
|
private:
|
|
base_atomic(const base_atomic &) /* = delete */ ;
|
|
void operator=(const base_atomic &) /* = delete */ ;
|
|
value_type v_;
|
|
};
|
|
|
|
#endif
|
|
|
|
/* generic */
|
|
|
|
template<typename T, bool Sign>
|
|
class base_atomic<T, void, 1, Sign>
|
|
{
|
|
typedef base_atomic this_type;
|
|
typedef T value_type;
|
|
typedef uint32_t storage_type;
|
|
public:
|
|
explicit base_atomic(value_type const& v) BOOST_NOEXCEPT : v_(0)
|
|
{
|
|
memcpy(&v_, &v, sizeof(value_type));
|
|
}
|
|
base_atomic(void) {}
|
|
|
|
void
|
|
store(value_type const& v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
storage_type tmp = 0;
|
|
memcpy(&tmp, &v, sizeof(value_type));
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"stw %1, %0\n"
|
|
: "+m" (v_)
|
|
: "r" (tmp)
|
|
);
|
|
ppc_fence_after_store(order);
|
|
}
|
|
|
|
value_type
|
|
load(memory_order order = memory_order_seq_cst) const volatile BOOST_NOEXCEPT
|
|
{
|
|
storage_type tmp;
|
|
__asm__ __volatile__ (
|
|
"lwz %0, %1\n"
|
|
"cmpw %0, %0\n"
|
|
"bne- 1f\n"
|
|
"1:\n"
|
|
: "=r"(tmp)
|
|
: "m"(v_)
|
|
: "cr0"
|
|
);
|
|
ppc_fence_after(order);
|
|
|
|
value_type v;
|
|
memcpy(&v, &tmp, sizeof(value_type));
|
|
return v;
|
|
}
|
|
|
|
value_type
|
|
exchange(value_type const& v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
storage_type tmp = 0, original;
|
|
memcpy(&tmp, &v, sizeof(value_type));
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y1\n"
|
|
"stwcx. %2,%y1\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "+Z"(v_)
|
|
: "b" (tmp)
|
|
: "cr0"
|
|
);
|
|
ppc_fence_after(order);
|
|
value_type res;
|
|
memcpy(&res, &original, sizeof(value_type));
|
|
return res;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_weak(
|
|
value_type & expected,
|
|
value_type const& desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
storage_type expected_s = 0, desired_s = 0;
|
|
memcpy(&expected_s, &expected, sizeof(value_type));
|
|
memcpy(&desired_s, &desired, sizeof(value_type));
|
|
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"lwarx %0,%y2\n"
|
|
"cmpw %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stwcx. %4,%y2\n"
|
|
"bne- 2f\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected_s), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected_s), "b" (desired_s)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
memcpy(&expected, &expected_s, sizeof(value_type));
|
|
return success;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_strong(
|
|
value_type & expected,
|
|
value_type const& desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
storage_type expected_s = 0, desired_s = 0;
|
|
memcpy(&expected_s, &expected, sizeof(value_type));
|
|
memcpy(&desired_s, &desired, sizeof(value_type));
|
|
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"0: lwarx %0,%y2\n"
|
|
"cmpw %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stwcx. %4,%y2\n"
|
|
"bne- 0b\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected_s), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected_s), "b" (desired_s)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
memcpy(&expected, &expected_s, sizeof(value_type));
|
|
return success;
|
|
}
|
|
|
|
bool
|
|
is_lock_free(void) const volatile BOOST_NOEXCEPT
|
|
{
|
|
return true;
|
|
}
|
|
|
|
BOOST_ATOMIC_DECLARE_BASE_OPERATORS
|
|
private:
|
|
base_atomic(const base_atomic &) /* = delete */ ;
|
|
void operator=(const base_atomic &) /* = delete */ ;
|
|
storage_type v_;
|
|
};
|
|
|
|
template<typename T, bool Sign>
|
|
class base_atomic<T, void, 2, Sign>
|
|
{
|
|
typedef base_atomic this_type;
|
|
typedef T value_type;
|
|
typedef uint32_t storage_type;
|
|
public:
|
|
explicit base_atomic(value_type const& v) BOOST_NOEXCEPT : v_(0)
|
|
{
|
|
memcpy(&v_, &v, sizeof(value_type));
|
|
}
|
|
|
|
base_atomic(void) {}
|
|
|
|
void
|
|
store(value_type const& v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
storage_type tmp = 0;
|
|
memcpy(&tmp, &v, sizeof(value_type));
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"stw %1, %0\n"
|
|
: "+m" (v_)
|
|
: "r" (tmp)
|
|
);
|
|
ppc_fence_after_store(order);
|
|
}
|
|
|
|
value_type
|
|
load(memory_order order = memory_order_seq_cst) const volatile BOOST_NOEXCEPT
|
|
{
|
|
storage_type tmp;
|
|
__asm__ __volatile__ (
|
|
"lwz %0, %1\n"
|
|
"cmpw %0, %0\n"
|
|
"bne- 1f\n"
|
|
"1:\n"
|
|
: "=r"(tmp)
|
|
: "m"(v_)
|
|
: "cr0"
|
|
);
|
|
ppc_fence_after(order);
|
|
|
|
value_type v;
|
|
memcpy(&v, &tmp, sizeof(value_type));
|
|
return v;
|
|
}
|
|
|
|
value_type
|
|
exchange(value_type const& v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
storage_type tmp = 0, original;
|
|
memcpy(&tmp, &v, sizeof(value_type));
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y1\n"
|
|
"stwcx. %2,%y1\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "+Z"(v_)
|
|
: "b" (tmp)
|
|
: "cr0"
|
|
);
|
|
ppc_fence_after(order);
|
|
value_type res;
|
|
memcpy(&res, &original, sizeof(value_type));
|
|
return res;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_weak(
|
|
value_type & expected,
|
|
value_type const& desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
storage_type expected_s = 0, desired_s = 0;
|
|
memcpy(&expected_s, &expected, sizeof(value_type));
|
|
memcpy(&desired_s, &desired, sizeof(value_type));
|
|
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"lwarx %0,%y2\n"
|
|
"cmpw %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stwcx. %4,%y2\n"
|
|
"bne- 2f\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected_s), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected_s), "b" (desired_s)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
memcpy(&expected, &expected_s, sizeof(value_type));
|
|
return success;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_strong(
|
|
value_type & expected,
|
|
value_type const& desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
storage_type expected_s = 0, desired_s = 0;
|
|
memcpy(&expected_s, &expected, sizeof(value_type));
|
|
memcpy(&desired_s, &desired, sizeof(value_type));
|
|
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"0: lwarx %0,%y2\n"
|
|
"cmpw %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stwcx. %4,%y2\n"
|
|
"bne- 0b\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected_s), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected_s), "b" (desired_s)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
memcpy(&expected, &expected_s, sizeof(value_type));
|
|
return success;
|
|
}
|
|
|
|
bool
|
|
is_lock_free(void) const volatile BOOST_NOEXCEPT
|
|
{
|
|
return true;
|
|
}
|
|
|
|
BOOST_ATOMIC_DECLARE_BASE_OPERATORS
|
|
private:
|
|
base_atomic(const base_atomic &) /* = delete */ ;
|
|
void operator=(const base_atomic &) /* = delete */ ;
|
|
storage_type v_;
|
|
};
|
|
|
|
template<typename T, bool Sign>
|
|
class base_atomic<T, void, 4, Sign>
|
|
{
|
|
typedef base_atomic this_type;
|
|
typedef T value_type;
|
|
typedef uint32_t storage_type;
|
|
public:
|
|
explicit base_atomic(value_type const& v) BOOST_NOEXCEPT : v_(0)
|
|
{
|
|
memcpy(&v_, &v, sizeof(value_type));
|
|
}
|
|
|
|
base_atomic(void) {}
|
|
|
|
void
|
|
store(value_type const& v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
storage_type tmp = 0;
|
|
memcpy(&tmp, &v, sizeof(value_type));
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"stw %1, %0\n"
|
|
: "+m" (v_)
|
|
: "r" (tmp)
|
|
);
|
|
ppc_fence_after_store(order);
|
|
}
|
|
|
|
value_type
|
|
load(memory_order order = memory_order_seq_cst) const volatile BOOST_NOEXCEPT
|
|
{
|
|
storage_type tmp;
|
|
__asm__ __volatile__ (
|
|
"lwz %0, %1\n"
|
|
"cmpw %0, %0\n"
|
|
"bne- 1f\n"
|
|
"1:\n"
|
|
: "=r"(tmp)
|
|
: "m"(v_)
|
|
: "cr0"
|
|
);
|
|
ppc_fence_after(order);
|
|
|
|
value_type v;
|
|
memcpy(&v, &tmp, sizeof(value_type));
|
|
return v;
|
|
}
|
|
|
|
value_type
|
|
exchange(value_type const& v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
storage_type tmp = 0, original;
|
|
memcpy(&tmp, &v, sizeof(value_type));
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"lwarx %0,%y1\n"
|
|
"stwcx. %2,%y1\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "+Z"(v_)
|
|
: "b" (tmp)
|
|
: "cr0"
|
|
);
|
|
ppc_fence_after(order);
|
|
value_type res;
|
|
memcpy(&res, &original, sizeof(value_type));
|
|
return res;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_weak(
|
|
value_type & expected,
|
|
value_type const& desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
storage_type expected_s = 0, desired_s = 0;
|
|
memcpy(&expected_s, &expected, sizeof(value_type));
|
|
memcpy(&desired_s, &desired, sizeof(value_type));
|
|
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"lwarx %0,%y2\n"
|
|
"cmpw %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stwcx. %4,%y2\n"
|
|
"bne- 2f\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected_s), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected_s), "b" (desired_s)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
memcpy(&expected, &expected_s, sizeof(value_type));
|
|
return success;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_strong(
|
|
value_type & expected,
|
|
value_type const& desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
storage_type expected_s = 0, desired_s = 0;
|
|
memcpy(&expected_s, &expected, sizeof(value_type));
|
|
memcpy(&desired_s, &desired, sizeof(value_type));
|
|
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"0: lwarx %0,%y2\n"
|
|
"cmpw %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stwcx. %4,%y2\n"
|
|
"bne- 0b\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected_s), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected_s), "b" (desired_s)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
memcpy(&expected, &expected_s, sizeof(value_type));
|
|
return success;
|
|
}
|
|
|
|
bool
|
|
is_lock_free(void) const volatile BOOST_NOEXCEPT
|
|
{
|
|
return true;
|
|
}
|
|
|
|
BOOST_ATOMIC_DECLARE_BASE_OPERATORS
|
|
private:
|
|
base_atomic(const base_atomic &) /* = delete */ ;
|
|
void operator=(const base_atomic &) /* = delete */ ;
|
|
storage_type v_;
|
|
};
|
|
|
|
#if defined(__powerpc64__)
|
|
|
|
template<typename T, bool Sign>
|
|
class base_atomic<T, void, 8, Sign>
|
|
{
|
|
typedef base_atomic this_type;
|
|
typedef T value_type;
|
|
typedef uint64_t storage_type;
|
|
public:
|
|
explicit base_atomic(value_type const& v) BOOST_NOEXCEPT : v_(0)
|
|
{
|
|
memcpy(&v_, &v, sizeof(value_type));
|
|
}
|
|
|
|
base_atomic(void) {}
|
|
|
|
void
|
|
store(value_type const& v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
storage_type tmp;
|
|
memcpy(&tmp, &v, sizeof(value_type));
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"std %1, %0\n"
|
|
: "+m" (v_)
|
|
: "r" (tmp)
|
|
);
|
|
ppc_fence_after_store(order);
|
|
}
|
|
|
|
value_type
|
|
load(memory_order order = memory_order_seq_cst) const volatile BOOST_NOEXCEPT
|
|
{
|
|
storage_type tmp;
|
|
__asm__ __volatile__ (
|
|
"ld %0, %1\n"
|
|
"cmpd %0, %0\n"
|
|
"bne- 1f\n"
|
|
"1:\n"
|
|
: "=r"(tmp)
|
|
: "m"(v_)
|
|
: "cr0"
|
|
);
|
|
ppc_fence_after(order);
|
|
|
|
value_type v;
|
|
memcpy(&v, &tmp, sizeof(value_type));
|
|
return v;
|
|
}
|
|
|
|
value_type
|
|
exchange(value_type const& v, memory_order order = memory_order_seq_cst) volatile BOOST_NOEXCEPT
|
|
{
|
|
storage_type tmp = 0, original;
|
|
memcpy(&tmp, &v, sizeof(value_type));
|
|
ppc_fence_before(order);
|
|
__asm__ (
|
|
"1:\n"
|
|
"ldarx %0,%y1\n"
|
|
"stdcx. %2,%y1\n"
|
|
"bne- 1b\n"
|
|
: "=&b" (original), "+Z"(v_)
|
|
: "b" (tmp)
|
|
: "cr0"
|
|
);
|
|
ppc_fence_after(order);
|
|
value_type res;
|
|
memcpy(&res, &original, sizeof(value_type));
|
|
return res;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_weak(
|
|
value_type & expected,
|
|
value_type const& desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
storage_type expected_s, desired_s;
|
|
memcpy(&expected_s, &expected, sizeof(value_type));
|
|
memcpy(&desired_s, &desired, sizeof(value_type));
|
|
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"ldarx %0,%y2\n"
|
|
"cmpd %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stdcx. %4,%y2\n"
|
|
"bne- 2f\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected_s), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected_s), "b" (desired_s)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
memcpy(&expected, &expected_s, sizeof(value_type));
|
|
return success;
|
|
}
|
|
|
|
bool
|
|
compare_exchange_strong(
|
|
value_type & expected,
|
|
value_type const& desired,
|
|
memory_order success_order,
|
|
memory_order failure_order) volatile BOOST_NOEXCEPT
|
|
{
|
|
storage_type expected_s, desired_s;
|
|
memcpy(&expected_s, &expected, sizeof(value_type));
|
|
memcpy(&desired_s, &desired, sizeof(value_type));
|
|
|
|
int success;
|
|
ppc_fence_before(success_order);
|
|
__asm__(
|
|
"0: ldarx %0,%y2\n"
|
|
"cmpd %0, %3\n"
|
|
"bne- 2f\n"
|
|
"stdcx. %4,%y2\n"
|
|
"bne- 0b\n"
|
|
"addi %1,0,1\n"
|
|
"1:"
|
|
|
|
BOOST_ATOMIC_ASM_SLOWPATH_CLEAR
|
|
: "=&b" (expected_s), "=&b" (success), "+Z"(v_)
|
|
: "b" (expected_s), "b" (desired_s)
|
|
: "cr0"
|
|
);
|
|
if (success)
|
|
ppc_fence_after(success_order);
|
|
else
|
|
ppc_fence_after(failure_order);
|
|
memcpy(&expected, &expected_s, sizeof(value_type));
|
|
return success;
|
|
}
|
|
|
|
bool
|
|
is_lock_free(void) const volatile BOOST_NOEXCEPT
|
|
{
|
|
return true;
|
|
}
|
|
|
|
BOOST_ATOMIC_DECLARE_BASE_OPERATORS
|
|
private:
|
|
base_atomic(const base_atomic &) /* = delete */ ;
|
|
void operator=(const base_atomic &) /* = delete */ ;
|
|
storage_type v_;
|
|
};
|
|
#endif
|
|
|
|
}
|
|
}
|
|
|
|
#define BOOST_ATOMIC_THREAD_FENCE 2
|
|
inline void
|
|
atomic_thread_fence(memory_order order)
|
|
{
|
|
switch(order) {
|
|
case memory_order_acquire:
|
|
__asm__ __volatile__ ("isync" ::: "memory");
|
|
break;
|
|
case memory_order_release:
|
|
#if defined(__powerpc64__)
|
|
__asm__ __volatile__ ("lwsync" ::: "memory");
|
|
break;
|
|
#endif
|
|
case memory_order_acq_rel:
|
|
case memory_order_seq_cst:
|
|
__asm__ __volatile__ ("sync" ::: "memory");
|
|
default:;
|
|
}
|
|
}
|
|
|
|
#define BOOST_ATOMIC_SIGNAL_FENCE 2
|
|
inline void
|
|
atomic_signal_fence(memory_order order)
|
|
{
|
|
switch(order) {
|
|
case memory_order_acquire:
|
|
case memory_order_release:
|
|
case memory_order_acq_rel:
|
|
case memory_order_seq_cst:
|
|
__asm__ __volatile__ ("" ::: "memory");
|
|
break;
|
|
default:;
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
#endif /* !defined(BOOST_ATOMIC_FORCE_FALLBACK) */
|
|
|
|
#endif
|