568 lines
19 KiB
C++
568 lines
19 KiB
C++
//===-- MipsISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the MIPS target.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-isel"
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#include "Mips.h"
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#include "MipsAnalyzeImmediate.h"
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#include "MipsMachineFunction.h"
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#include "MipsRegisterInfo.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetMachine.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "llvm/GlobalValue.h"
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#include "llvm/Instructions.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/Support/CFG.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MipsDAGToDAGISel - MIPS specific code to select MIPS machine
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// instructions for SelectionDAG operations.
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//===----------------------------------------------------------------------===//
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namespace {
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class MipsDAGToDAGISel : public SelectionDAGISel {
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/// TM - Keep a reference to MipsTargetMachine.
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MipsTargetMachine &TM;
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/// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
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/// make the right decision when generating code for different targets.
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const MipsSubtarget &Subtarget;
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public:
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explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
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SelectionDAGISel(tm),
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TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
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// Pass Name
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virtual const char *getPassName() const {
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return "MIPS DAG->DAG Pattern Instruction Selection";
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}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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private:
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// Include the pieces autogenerated from the target description.
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#include "MipsGenDAGISel.inc"
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/// getTargetMachine - Return a reference to the TargetMachine, casted
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/// to the target-specific type.
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const MipsTargetMachine &getTargetMachine() {
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return static_cast<const MipsTargetMachine &>(TM);
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}
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/// getInstrInfo - Return a reference to the TargetInstrInfo, casted
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/// to the target-specific type.
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const MipsInstrInfo *getInstrInfo() {
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return getTargetMachine().getInstrInfo();
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}
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SDNode *getGlobalBaseReg();
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std::pair<SDNode*, SDNode*> SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl,
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EVT Ty, bool HasLo, bool HasHi);
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SDNode *Select(SDNode *N);
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// Complex Pattern.
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bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Offset);
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// getImm - Return a target constant with the specified value.
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inline SDValue getImm(const SDNode *Node, unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
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}
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void ProcessFunctionAfterISel(MachineFunction &MF);
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bool ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&);
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void InitGlobalBaseReg(MachineFunction &MF);
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virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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char ConstraintCode,
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std::vector<SDValue> &OutOps);
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};
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}
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// Insert instructions to initialize the global base register in the
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// first MBB of the function. When the ABI is O32 and the relocation model is
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// PIC, the necessary instructions are emitted later to prevent optimization
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// passes from moving them.
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void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) {
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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if (!MipsFI->globalBaseRegSet())
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return;
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MachineBasicBlock &MBB = MF.front();
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MachineBasicBlock::iterator I = MBB.begin();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
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bool FixGlobalBaseReg = MipsFI->globalBaseRegFixed();
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if (Subtarget.isABI_O32() && FixGlobalBaseReg)
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// $gp is the global base register.
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V0 = V1 = GlobalBaseReg;
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else {
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const TargetRegisterClass *RC;
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RC = Subtarget.isABI_N64() ?
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Mips::CPU64RegsRegisterClass : Mips::CPURegsRegisterClass;
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V0 = RegInfo.createVirtualRegister(RC);
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V1 = RegInfo.createVirtualRegister(RC);
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}
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if (Subtarget.isABI_N64()) {
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MF.getRegInfo().addLiveIn(Mips::T9_64);
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MBB.addLiveIn(Mips::T9_64);
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// lui $v0, %hi(%neg(%gp_rel(fname)))
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// daddu $v1, $v0, $t9
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// daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
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const GlobalValue *FName = MF.getFunction();
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BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
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BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0).addReg(Mips::T9_64);
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BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
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} else if (MF.getTarget().getRelocationModel() == Reloc::Static) {
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// Set global register to __gnu_local_gp.
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//
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// lui $v0, %hi(__gnu_local_gp)
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// addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
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BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
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.addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
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BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
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.addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
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} else {
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MF.getRegInfo().addLiveIn(Mips::T9);
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MBB.addLiveIn(Mips::T9);
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if (Subtarget.isABI_N32()) {
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// lui $v0, %hi(%neg(%gp_rel(fname)))
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// addu $v1, $v0, $t9
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// addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
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const GlobalValue *FName = MF.getFunction();
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BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
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BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
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BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
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} else if (!MipsFI->globalBaseRegFixed()) {
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assert(Subtarget.isABI_O32());
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BuildMI(MBB, I, DL, TII.get(Mips::SETGP2), GlobalBaseReg)
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.addReg(Mips::T9);
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}
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}
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}
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bool MipsDAGToDAGISel::ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI,
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const MachineInstr& MI) {
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unsigned DstReg = 0, ZeroReg = 0;
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// Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
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if ((MI.getOpcode() == Mips::ADDiu) &&
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(MI.getOperand(1).getReg() == Mips::ZERO) &&
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(MI.getOperand(2).getImm() == 0)) {
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DstReg = MI.getOperand(0).getReg();
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ZeroReg = Mips::ZERO;
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} else if ((MI.getOpcode() == Mips::DADDiu) &&
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(MI.getOperand(1).getReg() == Mips::ZERO_64) &&
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(MI.getOperand(2).getImm() == 0)) {
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DstReg = MI.getOperand(0).getReg();
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ZeroReg = Mips::ZERO_64;
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}
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if (!DstReg)
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return false;
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// Replace uses with ZeroReg.
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for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
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E = MRI->use_end(); U != E; ++U) {
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MachineOperand &MO = U.getOperand();
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MachineInstr *MI = MO.getParent();
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// Do not replace if it is a phi's operand or is tied to def operand.
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if (MI->isPHI() || MI->isRegTiedToDefOperand(U.getOperandNo()))
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continue;
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MO.setReg(ZeroReg);
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}
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return true;
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}
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void MipsDAGToDAGISel::ProcessFunctionAfterISel(MachineFunction &MF) {
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InitGlobalBaseReg(MF);
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MachineRegisterInfo *MRI = &MF.getRegInfo();
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for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
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++MFI)
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for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I)
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ReplaceUsesWithZeroReg(MRI, *I);
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}
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bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
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bool Ret = SelectionDAGISel::runOnMachineFunction(MF);
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ProcessFunctionAfterISel(MF);
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return Ret;
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}
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/// getGlobalBaseReg - Output the instructions required to put the
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/// GOT address into a register.
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SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
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unsigned GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg();
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return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
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}
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/// ComplexPattern used on MipsInstrInfo
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/// Used on Mips Load/Store instructions
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bool MipsDAGToDAGISel::
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SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) {
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EVT ValTy = Addr.getValueType();
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// If Parent is an unaligned f32 load or store, select a (base + index)
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// floating point load/store instruction (luxc1 or suxc1).
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const LSBaseSDNode* LS = 0;
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if (Parent && (LS = dyn_cast<LSBaseSDNode>(Parent))) {
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EVT VT = LS->getMemoryVT();
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if (VT.getSizeInBits() / 8 > LS->getAlignment()) {
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assert(TLI.allowsUnalignedMemoryAccesses(VT) &&
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"Unaligned loads/stores not supported for this type.");
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if (VT == MVT::f32)
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return false;
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}
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}
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// if Address is FI, get the TargetFrameIndex.
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
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Offset = CurDAG->getTargetConstant(0, ValTy);
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return true;
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}
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// on PIC code Load GA
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if (Addr.getOpcode() == MipsISD::Wrapper) {
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Base = Addr.getOperand(0);
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Offset = Addr.getOperand(1);
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return true;
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}
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if (TM.getRelocationModel() != Reloc::PIC_) {
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if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress))
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return false;
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}
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// Addresses of the form FI+const or FI|const
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if (CurDAG->isBaseWithConstantOffset(Addr)) {
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
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if (isInt<16>(CN->getSExtValue())) {
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// If the first operand is a FI, get the TargetFI Node
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
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(Addr.getOperand(0)))
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
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else
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Base = Addr.getOperand(0);
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Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
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return true;
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}
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}
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// Operand is a result from an ADD.
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if (Addr.getOpcode() == ISD::ADD) {
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// When loading from constant pools, load the lower address part in
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// the instruction itself. Example, instead of:
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// lui $2, %hi($CPI1_0)
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// addiu $2, $2, %lo($CPI1_0)
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// lwc1 $f0, 0($2)
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// Generate:
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// lui $2, %hi($CPI1_0)
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// lwc1 $f0, %lo($CPI1_0)($2)
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if (Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
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SDValue LoVal = Addr.getOperand(1);
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if (isa<ConstantPoolSDNode>(LoVal.getOperand(0)) ||
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isa<GlobalAddressSDNode>(LoVal.getOperand(0))) {
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Base = Addr.getOperand(0);
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Offset = LoVal.getOperand(0);
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return true;
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}
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}
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// If an indexed floating point load/store can be emitted, return false.
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if (LS && (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
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Subtarget.hasMips32r2Or64())
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return false;
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}
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, ValTy);
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return true;
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}
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/// Select multiply instructions.
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std::pair<SDNode*, SDNode*>
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MipsDAGToDAGISel::SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, EVT Ty,
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bool HasLo, bool HasHi) {
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SDNode *Lo = 0, *Hi = 0;
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SDNode *Mul = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N->getOperand(0),
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N->getOperand(1));
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SDValue InFlag = SDValue(Mul, 0);
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if (HasLo) {
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Lo = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64, dl,
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Ty, MVT::Glue, InFlag);
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InFlag = SDValue(Lo, 1);
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}
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if (HasHi)
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Hi = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFHI : Mips::MFHI64, dl,
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Ty, InFlag);
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return std::make_pair(Lo, Hi);
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}
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/// Select instructions not customized! Used for
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/// expanded, promoted and normal instructions
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SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
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unsigned Opcode = Node->getOpcode();
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DebugLoc dl = Node->getDebugLoc();
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// Dump information about the Node being selected
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DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
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// If we have a custom node, we already have selected!
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if (Node->isMachineOpcode()) {
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DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
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return NULL;
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}
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///
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// Instruction Selection not handled by the auto-generated
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// tablegen selection should be handled here.
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///
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EVT NodeTy = Node->getValueType(0);
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unsigned MultOpc;
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switch(Opcode) {
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default: break;
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case ISD::SUBE:
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case ISD::ADDE: {
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SDValue InFlag = Node->getOperand(2), CmpLHS;
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unsigned Opc = InFlag.getOpcode(); (void)Opc;
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assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
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(Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
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"(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
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unsigned MOp;
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if (Opcode == ISD::ADDE) {
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CmpLHS = InFlag.getValue(0);
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MOp = Mips::ADDu;
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} else {
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CmpLHS = InFlag.getOperand(0);
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MOp = Mips::SUBu;
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}
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SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
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SDValue LHS = Node->getOperand(0);
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SDValue RHS = Node->getOperand(1);
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EVT VT = LHS.getValueType();
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SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
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SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
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SDValue(Carry,0), RHS);
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return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
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LHS, SDValue(AddCarry,0));
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}
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/// Mul with two results
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case ISD::SMUL_LOHI:
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case ISD::UMUL_LOHI: {
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if (NodeTy == MVT::i32)
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MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
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else
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MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT);
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std::pair<SDNode*, SDNode*> LoHi = SelectMULT(Node, MultOpc, dl, NodeTy,
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true, true);
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if (!SDValue(Node, 0).use_empty())
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ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
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if (!SDValue(Node, 1).use_empty())
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ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
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return NULL;
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}
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/// Special Muls
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case ISD::MUL: {
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// Mips32 has a 32-bit three operand mul instruction.
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if (Subtarget.hasMips32() && NodeTy == MVT::i32)
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break;
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return SelectMULT(Node, NodeTy == MVT::i32 ? Mips::MULT : Mips::DMULT,
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dl, NodeTy, true, false).first;
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}
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case ISD::MULHS:
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case ISD::MULHU: {
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if (NodeTy == MVT::i32)
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MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
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else
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MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT);
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return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;
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}
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// Get target GOT address.
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case ISD::GLOBAL_OFFSET_TABLE:
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return getGlobalBaseReg();
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case ISD::ConstantFP: {
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ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
|
|
if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
|
|
if (Subtarget.hasMips64()) {
|
|
SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
|
|
Mips::ZERO_64, MVT::i64);
|
|
return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero);
|
|
}
|
|
|
|
SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
|
|
Mips::ZERO, MVT::i32);
|
|
return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero,
|
|
Zero);
|
|
}
|
|
break;
|
|
}
|
|
|
|
case ISD::Constant: {
|
|
const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
|
|
unsigned Size = CN->getValueSizeInBits(0);
|
|
|
|
if (Size == 32)
|
|
break;
|
|
|
|
MipsAnalyzeImmediate AnalyzeImm;
|
|
int64_t Imm = CN->getSExtValue();
|
|
|
|
const MipsAnalyzeImmediate::InstSeq &Seq =
|
|
AnalyzeImm.Analyze(Imm, Size, false);
|
|
|
|
MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
|
|
DebugLoc DL = CN->getDebugLoc();
|
|
SDNode *RegOpnd;
|
|
SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
|
|
MVT::i64);
|
|
|
|
// The first instruction can be a LUi which is different from other
|
|
// instructions (ADDiu, ORI and SLL) in that it does not have a register
|
|
// operand.
|
|
if (Inst->Opc == Mips::LUi64)
|
|
RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
|
|
else
|
|
RegOpnd =
|
|
CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
|
|
CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
|
|
ImmOpnd);
|
|
|
|
// The remaining instructions in the sequence are handled here.
|
|
for (++Inst; Inst != Seq.end(); ++Inst) {
|
|
ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
|
|
MVT::i64);
|
|
RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
|
|
SDValue(RegOpnd, 0), ImmOpnd);
|
|
}
|
|
|
|
return RegOpnd;
|
|
}
|
|
|
|
case MipsISD::ThreadPointer: {
|
|
EVT PtrVT = TLI.getPointerTy();
|
|
unsigned RdhwrOpc, SrcReg, DestReg;
|
|
|
|
if (PtrVT == MVT::i32) {
|
|
RdhwrOpc = Mips::RDHWR;
|
|
SrcReg = Mips::HWR29;
|
|
DestReg = Mips::V1;
|
|
} else {
|
|
RdhwrOpc = Mips::RDHWR64;
|
|
SrcReg = Mips::HWR29_64;
|
|
DestReg = Mips::V1_64;
|
|
}
|
|
|
|
SDNode *Rdhwr =
|
|
CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
|
|
Node->getValueType(0),
|
|
CurDAG->getRegister(SrcReg, PtrVT));
|
|
SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
|
|
SDValue(Rdhwr, 0));
|
|
SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT);
|
|
ReplaceUses(SDValue(Node, 0), ResNode);
|
|
return ResNode.getNode();
|
|
}
|
|
}
|
|
|
|
// Select the default instruction
|
|
SDNode *ResNode = SelectCode(Node);
|
|
|
|
DEBUG(errs() << "=> ");
|
|
if (ResNode == NULL || ResNode == Node)
|
|
DEBUG(Node->dump(CurDAG));
|
|
else
|
|
DEBUG(ResNode->dump(CurDAG));
|
|
DEBUG(errs() << "\n");
|
|
return ResNode;
|
|
}
|
|
|
|
bool MipsDAGToDAGISel::
|
|
SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
|
|
std::vector<SDValue> &OutOps) {
|
|
assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
|
|
OutOps.push_back(Op);
|
|
return false;
|
|
}
|
|
|
|
/// createMipsISelDag - This pass converts a legalized DAG into a
|
|
/// MIPS-specific DAG, ready for instruction scheduling.
|
|
FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
|
|
return new MipsDAGToDAGISel(TM);
|
|
}
|