303 lines
7.6 KiB
LLVM
303 lines
7.6 KiB
LLVM
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; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s
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@A = global <4 x float> <float 0., float 1., float 2., float 3.>
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define void @test_sqrt(<4 x float>* %X) nounwind {
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; CHECK: test_sqrt:
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; CHECK: movw r1, :lower16:{{.*}}
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; CHECK: movt r1, :upper16:{{.*}}
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; CHECK: vldmia r1
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; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}}
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; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}}
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; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}}
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; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}}
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; CHECK: vstmia {{.*}}
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L.entry:
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%0 = load <4 x float>* @A, align 16
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%1 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %0)
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store <4 x float> %1, <4 x float>* %X, align 16
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ret void
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}
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declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) nounwind readonly
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define void @test_cos(<4 x float>* %X) nounwind {
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; CHECK: test_cos:
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; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
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; CHECK: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}}
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}cosf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}cosf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}cosf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}cosf
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; CHECK: vstmia {{.*}}
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L.entry:
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%0 = load <4 x float>* @A, align 16
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%1 = call <4 x float> @llvm.cos.v4f32(<4 x float> %0)
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store <4 x float> %1, <4 x float>* %X, align 16
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ret void
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}
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declare <4 x float> @llvm.cos.v4f32(<4 x float>) nounwind readonly
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define void @test_exp(<4 x float>* %X) nounwind {
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; CHECK: test_exp:
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; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
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; CHECK: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}}
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}expf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}expf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}expf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}expf
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; CHECK: vstmia {{.*}}
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L.entry:
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%0 = load <4 x float>* @A, align 16
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%1 = call <4 x float> @llvm.exp.v4f32(<4 x float> %0)
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store <4 x float> %1, <4 x float>* %X, align 16
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ret void
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}
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declare <4 x float> @llvm.exp.v4f32(<4 x float>) nounwind readonly
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define void @test_exp2(<4 x float>* %X) nounwind {
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; CHECK: test_exp2:
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; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
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; CHECK: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}}
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}exp2f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}exp2f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}exp2f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}exp2f
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; CHECK: vstmia {{.*}}
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L.entry:
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%0 = load <4 x float>* @A, align 16
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%1 = call <4 x float> @llvm.exp2.v4f32(<4 x float> %0)
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store <4 x float> %1, <4 x float>* %X, align 16
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ret void
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}
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declare <4 x float> @llvm.exp2.v4f32(<4 x float>) nounwind readonly
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define void @test_log10(<4 x float>* %X) nounwind {
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; CHECK: test_log10:
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; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
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; CHECK: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}}
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}log10f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}log10f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}log10f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}log10f
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; CHECK: vstmia {{.*}}
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L.entry:
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%0 = load <4 x float>* @A, align 16
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%1 = call <4 x float> @llvm.log10.v4f32(<4 x float> %0)
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store <4 x float> %1, <4 x float>* %X, align 16
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ret void
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}
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declare <4 x float> @llvm.log10.v4f32(<4 x float>) nounwind readonly
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define void @test_log(<4 x float>* %X) nounwind {
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; CHECK: test_log:
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; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
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; CHECK: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}}
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}logf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}logf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}logf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}logf
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; CHECK: vstmia {{.*}}
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L.entry:
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%0 = load <4 x float>* @A, align 16
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%1 = call <4 x float> @llvm.log.v4f32(<4 x float> %0)
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store <4 x float> %1, <4 x float>* %X, align 16
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ret void
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}
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declare <4 x float> @llvm.log.v4f32(<4 x float>) nounwind readonly
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define void @test_log2(<4 x float>* %X) nounwind {
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; CHECK: test_log2:
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; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
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; CHECK: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}}
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}log2f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}log2f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}log2f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}log2f
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; CHECK: vstmia {{.*}}
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L.entry:
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%0 = load <4 x float>* @A, align 16
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%1 = call <4 x float> @llvm.log2.v4f32(<4 x float> %0)
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store <4 x float> %1, <4 x float>* %X, align 16
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ret void
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}
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declare <4 x float> @llvm.log2.v4f32(<4 x float>) nounwind readonly
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define void @test_pow(<4 x float>* %X) nounwind {
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; CHECK: test_pow:
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; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
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; CHECK: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}}
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}powf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}powf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}powf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}powf
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; CHECK: vstmia {{.*}}
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L.entry:
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%0 = load <4 x float>* @A, align 16
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%1 = call <4 x float> @llvm.pow.v4f32(<4 x float> %0, <4 x float> <float 2., float 2., float 2., float 2.>)
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store <4 x float> %1, <4 x float>* %X, align 16
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ret void
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}
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declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>) nounwind readonly
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define void @test_powi(<4 x float>* %X) nounwind {
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; CHECK: test_powi:
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; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
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; CHECK: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia [[reg0]], {{.*}}
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; CHECK: vmul.f32 {{.*}}
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; CHECK: vstmia {{.*}}
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L.entry:
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%0 = load <4 x float>* @A, align 16
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%1 = call <4 x float> @llvm.powi.v4f32(<4 x float> %0, i32 2)
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store <4 x float> %1, <4 x float>* %X, align 16
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ret void
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}
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declare <4 x float> @llvm.powi.v4f32(<4 x float>, i32) nounwind readonly
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define void @test_sin(<4 x float>* %X) nounwind {
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; CHECK: test_sin:
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; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
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; CHECK: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}}
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}sinf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}sinf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}sinf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl {{.*}}sinf
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; CHECK: vstmia {{.*}}
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L.entry:
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%0 = load <4 x float>* @A, align 16
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%1 = call <4 x float> @llvm.sin.v4f32(<4 x float> %0)
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store <4 x float> %1, <4 x float>* %X, align 16
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ret void
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}
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declare <4 x float> @llvm.sin.v4f32(<4 x float>) nounwind readonly
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