653 lines
42 KiB
TableGen
653 lines
42 KiB
TableGen
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//===- PPCScheduleA2.td - PPC A2 Scheduling Definitions --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Primary reference:
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// A2 Processor User's Manual.
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// IBM (as updated in) 2010.
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//===----------------------------------------------------------------------===//
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// Functional units on the PowerPC A2 chip sets
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//
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def IU0to3_0 : FuncUnit; // Fetch unit 1 to 4 slot 1
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def IU0to3_1 : FuncUnit; // Fetch unit 1 to 4 slot 2
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def IU0to3_2 : FuncUnit; // Fetch unit 1 to 4 slot 3
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def IU0to3_3 : FuncUnit; // Fetch unit 1 to 4 slot 4
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def IU4_0 : FuncUnit; // Instruction buffer slot 1
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def IU4_1 : FuncUnit; // Instruction buffer slot 2
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def IU4_2 : FuncUnit; // Instruction buffer slot 3
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def IU4_3 : FuncUnit; // Instruction buffer slot 4
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def IU4_4 : FuncUnit; // Instruction buffer slot 5
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def IU4_5 : FuncUnit; // Instruction buffer slot 6
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def IU4_6 : FuncUnit; // Instruction buffer slot 7
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def IU4_7 : FuncUnit; // Instruction buffer slot 8
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def IU5 : FuncUnit; // Dependency resolution
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def IU6 : FuncUnit; // Instruction issue
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def RF0 : FuncUnit;
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def XRF1 : FuncUnit;
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def XEX1 : FuncUnit; // Execution stage 1 for the XU pipeline
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def XEX2 : FuncUnit; // Execution stage 2 for the XU pipeline
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def XEX3 : FuncUnit; // Execution stage 3 for the XU pipeline
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def XEX4 : FuncUnit; // Execution stage 4 for the XU pipeline
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def XEX5 : FuncUnit; // Execution stage 5 for the XU pipeline
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def XEX6 : FuncUnit; // Execution stage 6 for the XU pipeline
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def FRF1 : FuncUnit;
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def FEX1 : FuncUnit; // Execution stage 1 for the FU pipeline
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def FEX2 : FuncUnit; // Execution stage 2 for the FU pipeline
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def FEX3 : FuncUnit; // Execution stage 3 for the FU pipeline
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def FEX4 : FuncUnit; // Execution stage 4 for the FU pipeline
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def FEX5 : FuncUnit; // Execution stage 5 for the FU pipeline
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def FEX6 : FuncUnit; // Execution stage 6 for the FU pipeline
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def CR_Bypass : Bypass; // The bypass for condition regs.
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//def GPR_Bypass : Bypass; // The bypass for general-purpose regs.
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//def FPR_Bypass : Bypass; // The bypass for floating-point regs.
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//
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// This file defines the itinerary class data for the PPC A2 processor.
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//
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//===----------------------------------------------------------------------===//
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def PPCA2Itineraries : ProcessorItineraries<
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3,
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IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7,
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IU5, IU6, RF0, XRF1, XEX1, XEX2, XEX3, XEX4, XEX5, XEX6,
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FRF1, FEX1, FEX2, FEX3, FEX4, FEX5, FEX6],
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[CR_Bypass, GPR_Bypass, FPR_Bypass], [
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InstrItinData<IntGeneral , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
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InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
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InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[10, 7, 7],
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntCompare , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
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InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
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InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[10, 7, 7],
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[CR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntDivW , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
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InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
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InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
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InstrStage<1, [XEX5]>, InstrStage<38, [XEX6]>],
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[53, 7, 7],
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[NoBypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntMFFS , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
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InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
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InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[10, 7, 7],
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntMTFSB0 , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
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InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
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InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[10, 7, 7],
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntMulHW , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
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InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
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InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[14, 7, 7],
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntMulHWU , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
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InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
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InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[14, 7, 7],
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntMulLI , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
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InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
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InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[15, 7, 7],
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntRotate , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
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InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
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InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[10, 7, 7],
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntShift , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
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InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
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InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[10, 7, 7],
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntTrapW , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
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InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
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InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[10, 7, 7],
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<BrB , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
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InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
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InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[15, 7, 7],
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[NoBypass, GPR_Bypass]>,
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InstrItinData<BrCR , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
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InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
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InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[10, 7, 7],
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[CR_Bypass, CR_Bypass, CR_Bypass]>,
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InstrItinData<BrMCR , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
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InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
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InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[10, 7, 7],
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[CR_Bypass, CR_Bypass, CR_Bypass]>,
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InstrItinData<BrMCRX , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
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InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
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InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[10, 7, 7],
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[CR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStDCBA , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
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InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
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InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[13, 11],
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStDCBF , [InstrStage<4,
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[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
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InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
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IU4_4, IU4_5, IU4_6, IU4_7]>,
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InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
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InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
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InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
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InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
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InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
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[13, 11],
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[NoBypass, GPR_Bypass]>,
|
||
|
|
InstrItinData<LdStDCBI , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||
|
|
[13, 11],
|
||
|
|
[NoBypass, GPR_Bypass]>,
|
||
|
|
InstrItinData<LdStLoad , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||
|
|
[14, 7],
|
||
|
|
[GPR_Bypass, GPR_Bypass]>,
|
||
|
|
InstrItinData<LdStStore , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||
|
|
[13, 7],
|
||
|
|
[GPR_Bypass, GPR_Bypass]>,
|
||
|
|
InstrItinData<LdStICBI , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||
|
|
[14, 7],
|
||
|
|
[NoBypass, GPR_Bypass]>,
|
||
|
|
InstrItinData<LdStUX , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||
|
|
[14, 7, 7],
|
||
|
|
[NoBypass, FPR_Bypass, FPR_Bypass]>,
|
||
|
|
InstrItinData<LdStLFD , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||
|
|
[14, 7, 7],
|
||
|
|
[FPR_Bypass, GPR_Bypass, GPR_Bypass]>,
|
||
|
|
InstrItinData<LdStLFDU , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||
|
|
[14, 7, 7],
|
||
|
|
[FPR_Bypass, GPR_Bypass, GPR_Bypass]>,
|
||
|
|
InstrItinData<LdStLHA , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||
|
|
[14, 7],
|
||
|
|
[NoBypass, GPR_Bypass]>,
|
||
|
|
InstrItinData<LdStLMW , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||
|
|
[14, 7],
|
||
|
|
[NoBypass, GPR_Bypass]>,
|
||
|
|
InstrItinData<LdStLWARX , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<13, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||
|
|
[26, 7],
|
||
|
|
[NoBypass, GPR_Bypass]>,
|
||
|
|
InstrItinData<LdStSTD , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||
|
|
[13, 7],
|
||
|
|
[GPR_Bypass, GPR_Bypass]>,
|
||
|
|
InstrItinData<LdStSTDCX , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<13, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||
|
|
[26, 7],
|
||
|
|
[NoBypass, GPR_Bypass]>,
|
||
|
|
InstrItinData<LdStSTD , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||
|
|
[13, 7],
|
||
|
|
[GPR_Bypass, GPR_Bypass]>,
|
||
|
|
InstrItinData<LdStSTDCX , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<13, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||
|
|
[26, 7],
|
||
|
|
[NoBypass, GPR_Bypass]>,
|
||
|
|
InstrItinData<LdStSTWCX , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<13, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||
|
|
[26, 7],
|
||
|
|
[NoBypass, GPR_Bypass]>,
|
||
|
|
InstrItinData<LdStSync , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<12, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>]>,
|
||
|
|
InstrItinData<SprISYNC , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>]>,
|
||
|
|
InstrItinData<SprMFSR , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||
|
|
[15, 7],
|
||
|
|
[GPR_Bypass, NoBypass]>,
|
||
|
|
InstrItinData<SprMTMSR , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||
|
|
[15, 7],
|
||
|
|
[NoBypass, GPR_Bypass]>,
|
||
|
|
InstrItinData<SprMTSR , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||
|
|
[15, 7],
|
||
|
|
[NoBypass, GPR_Bypass]>,
|
||
|
|
InstrItinData<SprTLBSYNC , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>]>,
|
||
|
|
InstrItinData<SprMFCR , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||
|
|
[10, 7],
|
||
|
|
[GPR_Bypass, CR_Bypass]>,
|
||
|
|
InstrItinData<SprMFMSR , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||
|
|
[15, 7],
|
||
|
|
[GPR_Bypass, NoBypass]>,
|
||
|
|
InstrItinData<SprMFSPR , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||
|
|
[15, 7],
|
||
|
|
[NoBypass, GPR_Bypass]>,
|
||
|
|
InstrItinData<SprMFTB , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>],
|
||
|
|
[29, 7],
|
||
|
|
[NoBypass, GPR_Bypass]>,
|
||
|
|
InstrItinData<SprMTSPR , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||
|
|
[15, 7],
|
||
|
|
[NoBypass, GPR_Bypass]>,
|
||
|
|
InstrItinData<SprMTSRIN , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>],
|
||
|
|
[29, 7],
|
||
|
|
[NoBypass, GPR_Bypass]>,
|
||
|
|
InstrItinData<SprRFI , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>],
|
||
|
|
[29, 7],
|
||
|
|
[NoBypass, GPR_Bypass]>,
|
||
|
|
InstrItinData<SprSC , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||
|
|
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||
|
|
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||
|
|
InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>],
|
||
|
|
[29, 7],
|
||
|
|
[NoBypass, GPR_Bypass]>,
|
||
|
|
InstrItinData<FPGeneral , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>,
|
||
|
|
InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>,
|
||
|
|
InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>,
|
||
|
|
InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
|
||
|
|
[15, 7, 7],
|
||
|
|
[FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
|
||
|
|
InstrItinData<FPCompare , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>,
|
||
|
|
InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>,
|
||
|
|
InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>,
|
||
|
|
InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
|
||
|
|
[13, 7, 7],
|
||
|
|
[CR_Bypass, FPR_Bypass, FPR_Bypass]>,
|
||
|
|
InstrItinData<FPDivD , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<71, [FRF1], 0>,
|
||
|
|
InstrStage<71, [FEX1], 0>,
|
||
|
|
InstrStage<71, [FEX2], 0>,
|
||
|
|
InstrStage<71, [FEX3], 0>,
|
||
|
|
InstrStage<71, [FEX4], 0>,
|
||
|
|
InstrStage<71, [FEX5], 0>,
|
||
|
|
InstrStage<71, [FEX6]>],
|
||
|
|
[86, 7, 7],
|
||
|
|
[NoBypass, FPR_Bypass, FPR_Bypass]>,
|
||
|
|
InstrItinData<FPDivS , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<58, [FRF1], 0>,
|
||
|
|
InstrStage<58, [FEX1], 0>,
|
||
|
|
InstrStage<58, [FEX2], 0>,
|
||
|
|
InstrStage<58, [FEX3], 0>,
|
||
|
|
InstrStage<58, [FEX4], 0>,
|
||
|
|
InstrStage<58, [FEX5], 0>,
|
||
|
|
InstrStage<58, [FEX6]>],
|
||
|
|
[73, 7, 7],
|
||
|
|
[NoBypass, FPR_Bypass, FPR_Bypass]>,
|
||
|
|
InstrItinData<FPSqrt , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<68, [FRF1], 0>,
|
||
|
|
InstrStage<68, [FEX1], 0>,
|
||
|
|
InstrStage<68, [FEX2], 0>,
|
||
|
|
InstrStage<68, [FEX3], 0>,
|
||
|
|
InstrStage<68, [FEX4], 0>,
|
||
|
|
InstrStage<68, [FEX5], 0>,
|
||
|
|
InstrStage<68, [FEX6]>],
|
||
|
|
[86, 7], // FIXME: should be [86, 7] for double
|
||
|
|
// and [82, 7] for single. Likewise,
|
||
|
|
// the FEX? cycle count should be 68
|
||
|
|
// for double and 64 for single.
|
||
|
|
[NoBypass, FPR_Bypass]>,
|
||
|
|
InstrItinData<FPFused , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>,
|
||
|
|
InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>,
|
||
|
|
InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>,
|
||
|
|
InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
|
||
|
|
[15, 7, 7, 7],
|
||
|
|
[FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
|
||
|
|
InstrItinData<FPRes , [InstrStage<4,
|
||
|
|
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||
|
|
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||
|
|
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||
|
|
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||
|
|
InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>,
|
||
|
|
InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>,
|
||
|
|
InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>,
|
||
|
|
InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
|
||
|
|
[15, 7],
|
||
|
|
[FPR_Bypass, FPR_Bypass]>
|
||
|
|
]>;
|